I am using the GSFI to access a MT25QU256ABA flash in order to write and erase FPGA images, that will be loaded via the Remote Update IP.
Writing and erasing JIC files with the Programmer/SFL Design works fine as well as writing via the GSFI.
The problem comes up as soon as I try to erase multiple sectors. Erasing the first sector works fine:
1) Set the command register to 0xDC (-> 4 byte erase)
2) Set the address register to the base address of the sector
3) Start operation
Then I start to cyclical read the flag status register (command 0x70) and check whether Bit 7 equals 1. After about 7 ms the Bit is set to 1, the sector is erased and I proceed to the next sector.
But this time, after doing the 3 steps mentioned above, the READY Bit in the flag status register is immediately set but the sector is not even erased. As if by setting the command and address and starting the operation the IP core wouldn't even change it's state to busy. Did the core "lie" to me when it changed it's state to READY after 7 ms?
This makes it hard for me to implement a routine that erases multiple sectors at once, because I don't know when the flash is ready for me to proceed to the next sector. Is there no other way than to add a wait time? Why does the READY Bit only work for the first sector? I have even tried to do the clear flag status command (0x50) after I have gotten a READY = 1 but that didn't help either.
Has someone else come accross this problem?
Thank you very much in advance!
yes, I performed a single Write Enable (command = 0x06) to the flash before the first Sector Erase.
Do I need to do that previous to every erase?