Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
739 Views

Problem in read cycle with ddr2 controller

Hello, 

i am developing a board using Cyclone 2 and interface with DDR2 MT47H64M16HR-3 using DDR2 Megacore in SOPC (not High performance one), with CL = 5, WL = 4. It seems that there is no problem with write cycle, but in read cycle, the data output from DDRT2 is always later than it's DQS about 1/2 clock so the first 16bits always is 0xffff. 

And the thing is, after read command (CS,CAS = 0), there is always a command with CS,WE = 0, I have a look at DDR2 spec. and found no detail about this comman, does it NOP command. 

Have anybody see this problem, could you give me an advice? 

I attach the picture of waveform of problem. 

Thanks a lot. 

Thanh
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
25 Views

There is no problem! First DQS toggling is known as Preamble and it is a requirement