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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Problem understanding de-interlacer core.

Honored Contributor II


I'm trying to implement the De-interlacer core with the following spec, 

Algorithm - Bob scanline duplication with no buffering. 

Output frame rate = Input field rate. 

Clock frequency = 25 MHz. 


I have assumed the output to be as in the picture (pl refer attachment - output.jpg) 

With reference to that I expected one pixel output per clock but when I simulated it in Modelsim I found the output to be one pixel for 4 clock cycle (Pl refer attachement pic5, pic6, pic7). 

pic5 - zoom out of initial packet formation. 

pic6 - zoom in of packet formation. 

pic7 - after a few clock cycle from the start of packet. 


The pic also contains the generation of avalon-ST signal (SOP,EOP,VALID etc)...Kindly let me know if i'm generating proper signals. 

also regarding the packet formation for avalon-st, should i make each line in a frame as a packet or can i take the entire frame as one single packet? 


I wanted to know if there are any data sheet or documentation available on the Deinterlacer core or any timing diagram regarding the functionality of the core. I already went through VIP user guide.  


Thanks and regards, 

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Honored Contributor II

Hello Arthes, 

it's passed a while from your post so I think that now you are definitely working on something else :) 

Anyway, I'm working with something similar. I could tell you that a packet information is related to an entire frame and not a sinlgle line. In fact, if you look at control packet just previous to a video packet, you would read information about the frame that is going to come (like width, height, interlaced or progressive ecc.) 

I'd like to ask you: did the deinterlacer with bob algorithm work well? Have you tested it? 

Thank you
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