Problem using Tranceiver Toolkit on Cyclone V Soc Kit

[MEmel1]

I've a problem receiving data on tranceiver control link in loopback mode. Tranceiver tx side is green, but receive side is yellow indicating that no incoming data is present, as far as i understand.

There are different options avaliable such as use preamble, different pattern generation on tx side, enable word aligner on the rx side, etc., but no comprehensive docs on how to use them. At least I failed to find one.

So, I'd be grateful for any piece of information on how to go about debugging my problem.

P.S. I'm working in Quartus 13.1 and my project in Qsys is based on Altera's example cv_GX_1ch_40b_3125mbps, which I modified for Cyclone V Soc Kit.

The modifications are:

1) the initial sys_clk of 100MHz and ref_clk of 125MHz are replaced with one ref_clk of 100MHz, that clocks every part of the design.

2) the tranceiver PMA-PCS and FPGA fabric bus width reduced to 8

3) the tranceiver bitrate is also reduced to 800 bps

4) word aligner pattern length is 8, pattern itself is 11111001

5) ST_DATA_W parameter in data_pattern_generator and checker is 32

[Nathan_R_Intel]

Hie, The design attached in the Cyclone V SOC Kit installer package was not intended to be used with Transceiver Toolkit. It was intended to be used with the Board test System. Hence, please try using a design targeted for Transceiver Toolkit. We have a reference design Transceiver Toolkit for Cyclone V. Please use this reference design and migrate over to Cyclone V SOC Devkit. This should ensure your Transceiver Toolkit is working correctly. Please get the Cyclone V Transceiver Toolkit design from following link: https://fpgawiki.intel.com/wiki/Transceiver_Toolkit As for using Transceiver Toolkit, you can refer to the following How-To-Video. Hope this helps with your issue. https://www.youtube.com/watch?v=0oO1RFa-4Xk Regards, Nathan

[MEmel1]

Hi, Nathan

Thanks for your reply!

As far as I understand, I did exactly what you suggested. I took cv_GX_1ch_40b_3125mbps reference design for Cyclone V GX and modified it for Cyclone V SoC Devkit, as I mentioned in my previous post.

As for the video, it focuses on using ADC Toolkit for MAX devices. Few things concerning basic design flow in Qsys were useful, but I can't see how is that relevant to Tranceiver Toolkit and my issue especially.

[Nathan_R_Intel]

Hie, I provided the wrong youtube link. Please refer to the following link. It is showing how to use Transceiver Toolkit in Cyclone V. https://www.youtube.com/watch?v=vlDr1KJDRjg&t=1s Please get your Transceiver Toolkit design to work as shown in How To Video above. Then you can change the transceiver configuration per your requirement and check if the problem persist. Regards, Nathan

[MEmel1]

Thanks for the video, Nathan.

Is where any way to download the design from this demo?

[Nathan_R_Intel]

The design used in this demo should be similar to the design in the Intel-Wiki. Do let me know otherwise, I will need to re-create a design for you. https://fpgawiki.intel.com/wiki/Transceiver_Toolkit Regards, Nathan