I've a problem receiving data on tranceiver control link in loopback mode. Tranceiver tx side is green, but receive side is yellow indicating that no incoming data is present, as far as i understand.
There are different options avaliable such as use preamble, different pattern generation on tx side, enable word aligner on the rx side, etc., but no comprehensive docs on how to use them. At least I failed to find one.
So, I'd be grateful for any piece of information on how to go about debugging my problem.
P.S. I'm working in Quartus 13.1 and my project in Qsys is based on Altera's example cv_GX_1ch_40b_3125mbps, which I modified for Cyclone V Soc Kit.
The modifications are:
1) the initial sys_clk of 100MHz and ref_clk of 125MHz are replaced with one ref_clk of 100MHz, that clocks every part of the design.
2) the tranceiver PMA-PCS and FPGA fabric bus width reduced to 8
3) the tranceiver bitrate is also reduced to 800 bps
4) word aligner pattern length is 8, pattern itself is 11111001
5) ST_DATA_W parameter in data_pattern_generator and checker is 32
Thanks for your reply!
As far as I understand, I did exactly what you suggested. I took cv_GX_1ch_40b_3125mbps reference design for Cyclone V GX and modified it for Cyclone V SoC Devkit, as I mentioned in my previous post.
As for the video, it focuses on using ADC Toolkit for MAX devices. Few things concerning basic design flow in Qsys were useful, but I can't see how is that relevant to Tranceiver Toolkit and my issue especially.