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Problem with Avalon-St for deinterlacing

Honored Contributor II


I'm new to altera and 'm working on a de-interlacing core which is available in the Megacore wizard. 

I wanted to know if it was possible to simulate the core (in modelsim) by just writing a simple wrapper. 

I did go through the AVALON-ST protocol, and tried simulating the core. 



In my setup I have my test bench as the Source and the De-interlacing core as the Sink. The de-interlacing core was generated from the megacore function and was instantiated in the test_bench file. 

As per the Avalon-St protocol, the Sink first invokes the ready signal (din_ready), then based on the ready_latency i have to assert the valid (din_valid) from the test bench, then go along with the SOP and EOP... 

But when I tried simulating the core, the core doesn't assert the ready (din_ready) signal at all. Should i add any libraries to modelsim for simulating megacore funtions?? 

BTW I'm using BOB scan line algorithm with no buffering. 

Can anyone suggest me where I'm going wrong. 


Thanks and regards, 

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