FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Problem with FIR compiler - DSP Builder 12.1 - MegaCore Function Generation Error

Altera_Forum
Honored Contributor II
1,172 Views

Hello, 

 

I do not manage to generate in DSP Builder FIR compiler instances with coefficients different than the default ones (lowpass). 

 

I am using Matlab R2011a (Linux), DSP Builder 12.1sp1 and as target Arria II GX. 

 

If I instantiate a new FIR compiler and I do not change its parameters, the IP is correctly generated. If I try to change its coefficients (wth my coefficients or for example by using the high pass default coefficients), then I got the following error: 

 

megacore function generation error 

ip functional simulation model creation failed. the following error was returned: 

error: quartus ii 32-bit analysis and synthesis was unsuccessfull. 51 errors, 1 warning. 

 

I noted that the launch_iptb.sh generated is different in the two cases: 

 

 

fir generated: "/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin/ip_toolbench.exe" -simgen_enable.language:vhdl -simgen_enable.enabled:1 -silent -flow_dir:/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin -alt_flow_dir:/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin -simgen.family:"arria ii gx" -core_dir:/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/ip_toolbench -wizard:fir_compiler "/home/test/dspbuilder_sat_dsp_import/fir_after_cic_i.vhd"  

 

 

fir not generated: "/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin/ip_toolbench.exe" -simgen.parameter:simgen_preserve_port_order=on,simgen_optimization=all -quartus_rootdir:"/opt/tools/altera12.1sp1/quartus" -dsp -flow_dir:"/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin" -alt_flow_dir:"/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin" -dsp_builder_dir:"/home/test/dspbuilder_sat_dsp_import" -core_dir:"/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/ip_toolbench" -simgen.family:"arria ii gx" -wizard:fir_compiler "/home/test/dspbuilder_sat_dsp_import/fir_after_cic_q.vhd" -debug:3  

 

Moreover in the launch_iptb.txt files there are errors like: 

 

info (281010): generating sgate simulator netlist using simgen 

simgen_progress start of model generation -- 0% complete 

simgen_progress phase 1 : internal objects created -- 25% complete 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|dataa is of width 11 but the range indices are (15, 15) cause : the range indices are illegal, either the higher index is more than the width of the port or the lower index is less than 0. 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|dataa of width 11 is being made an assignment of simgen|dffe inst n0l1100l|dataout|range--w_dataout_range14023w in the range 15 to 15 cause : an attempt was made to assign a bit that is not there in the port. 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|datab is of width 11 but the range indices are (15, 15) cause : the range indices are illegal, either the higher index is more than the width of the port or the lower index is less than 0. 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|datab of width 11 is being made an assignment of constant value 0 in the range 15 to 15 cause : an attempt was made to assign a bit that is not there in the port. 

... 

 

 

I hope someone has already met and solved this kind of problem. I did not find any advice in internet. 

 

Please consider I cannot pass to a different DSP Builder version. 

 

Any help or advice is more than appreciated... 

 

Thanks 

A_G76
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
94 Views

Dear sir: 

Is your question solved?  

 

 

 

 

--- Quote Start ---  

Hello, 

 

I do not manage to generate in DSP Builder FIR compiler instances with coefficients different than the default ones (lowpass). 

 

I am using Matlab R2011a (Linux), DSP Builder 12.1sp1 and as target Arria II GX. 

 

If I instantiate a new FIR compiler and I do not change its parameters, the IP is correctly generated. If I try to change its coefficients (wth my coefficients or for example by using the high pass default coefficients), then I got the following error: 

 

megacore function generation error 

ip functional simulation model creation failed. the following error was returned: 

error: quartus ii 32-bit analysis and synthesis was unsuccessfull. 51 errors, 1 warning. 

 

I noted that the launch_iptb.sh generated is different in the two cases: 

 

 

fir generated: "/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin/ip_toolbench.exe" -simgen_enable.language:vhdl -simgen_enable.enabled:1 -silent -flow_dir:/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin -alt_flow_dir:/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin -simgen.family:"arria ii gx" -core_dir:/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/ip_toolbench -wizard:fir_compiler "/home/test/dspbuilder_sat_dsp_import/fir_after_cic_i.vhd"  

 

 

fir not generated: "/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin/ip_toolbench.exe" -simgen.parameter:simgen_preserve_port_order=on,simgen_optimization=all -quartus_rootdir:"/opt/tools/altera12.1sp1/quartus" -dsp -flow_dir:"/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin" -alt_flow_dir:"/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/../../common/ip_toolbench/v1.3.0/bin" -dsp_builder_dir:"/home/test/dspbuilder_sat_dsp_import" -core_dir:"/opt/tools/altera12.1sp1/ip/altera/fir_compiler/lib/ip_toolbench" -simgen.family:"arria ii gx" -wizard:fir_compiler "/home/test/dspbuilder_sat_dsp_import/fir_after_cic_q.vhd" -debug:3  

 

Moreover in the launch_iptb.txt files there are errors like: 

 

info (281010): generating sgate simulator netlist using simgen 

simgen_progress start of model generation -- 0% complete 

simgen_progress phase 1 : internal objects created -- 25% complete 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|dataa is of width 11 but the range indices are (15, 15) cause : the range indices are illegal, either the higher index is more than the width of the port or the lower index is less than 0. 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|dataa of width 11 is being made an assignment of simgen|dffe inst n0l1100l|dataout|range--w_dataout_range14023w in the range 15 to 15 cause : an attempt was made to assign a bit that is not there in the port. 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|datab is of width 11 but the range indices are (15, 15) cause : the range indices are illegal, either the higher index is more than the width of the port or the lower index is less than 0. 

error (281011): mgl_internal_error: port simgen|mux21 inst nl11l1oi|datab of width 11 is being made an assignment of constant value 0 in the range 15 to 15 cause : an attempt was made to assign a bit that is not there in the port. 

... 

 

 

I hope someone has already met and solved this kind of problem. I did not find any advice in internet. 

 

Please consider I cannot pass to a different DSP Builder version. 

 

Any help or advice is more than appreciated... 

 

Thanks 

A_G76 

--- Quote End ---  

Altera_Forum
Honored Contributor II
94 Views

Hi stephen_zcy, 

 

my problem was solved by an Altera FAE with a specific ad hoc patch. Now it works fine, thanks.
Reply