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Problems with PCI express IP Compiler and Pin Planner

Altera_Forum
Honored Contributor II
791 Views

Hi, I began to study PCI Express system in order to implement on a FPGA. I'm using Stratix II GX development Kit board and i already am at the point to connect the pins of the FPGA using the Pin Planner Editor. The problem is that i don't know how to relate the signals in the top level generated by de PCI Express Ip Compiler and the correct pins on the FPGA. I really appreciate if anybody can give me a correct assignment file. The target FPGA is the EP2SGX90FF1508C3. Thank you very much in advance

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Altera_Forum
Honored Contributor II
84 Views

First, you need refer to Figure 5–41 of IP Compiler for PCIe User Guide to understand the PCIe Rx/Tx transceiver channels location assignments. 

The assignment is like this: 

Transceiver Ch0 --> PCIe Rx0/TX0 

Transceiver Ch1 --> PCIe Rx1/TX1 

Transceiver Ch2 --> PCIe Rx2/TX2 

Transceiver Ch3 --> PCIe Rx3/TX3 

... and so on 

 

The refer to the Stratix II device pin-out files to know the pin location assignment.
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