Community
cancel
Showing results for 
Search instead for 
Did you mean: 
FeatureGNchiP
Employee
296 Views

Ptile PCIe to Htile PCIe Migration

Planned to Migrate Ptile PCIe to Htile PCIe, but the below Ptile PCIe signals not availble in Htile PCIe IP. Application layer uses the p0_rx_st_hdr_o signal, so need to know how to handle this in Htile IP.

>>>>>>>>>>>>>>>>>

p0_rx_st_hdr_o       
p0_rx_st_tlp_prfx_o  
p0_rx_st_bar_range_o 
p0_rx_st_tlp_abort_o 
p0_rx_par_err_o   

>>>>>>>>>>>>>>>>>

Thanks!   

0 Kudos
8 Replies
Rahul_S_Intel1
Employee
287 Views

Hi ,

 Kindly allow me some time to look on your issue

Rahul_S_Intel1
Employee
284 Views

Hi ,

 I understand your concern, to clarify your question.

The Ptile supports different type of configuration (1x16, 2x8 or 4x4) , so the value of below signal will change depends up on the configration.

p0_rx_st_data_o[127:0], p0_rx_st_hdr_o[127:0] and
p0_rx_st_tlp_prfx_o[31:0].

Ref:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf

page no:41

But the same is not been in the S10 H tile device

Ref:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-s10-pcie-avs...

Page no:52

Tags (1)
FeatureGNchiP
Employee
280 Views

Hi,

   we need x8 configuration, so in Ptile the P1 interface driven by "0" and only P0 interface is used for application layer transaction.

>>>> H tile bus width details >>>>

p0_rx_st_data_o[256:0], p0_rx_st_hdr_o[127:0] and
p0_rx_st_tlp_prfx_o[31:0].

>>>>>>>>>>>>>>>>>>>>>>>>>>>

While migrate to Htile we are choosing Gen3x8,256bit configuration. Am also referring the documents which you shared in this thread. In Htile, seems like header information is available in the data bus itself.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-s10-pcie-avs... [page no : 53.]

If my understanding is correct, I need to add glue logic to handle this variation or any adapter is availble to separate the header information from the data bus.

If my understanding is not correct, please provide the correct direction.

Rahul_S_Intel1
Employee
255 Views

Hi , 

Kindy note that , the architecture of P tile Avalon ST PCIe is different from the H Tile Avalon ST PCIe Ip. And the migration from Ptile to H tile you need separate logic.

 Kindly find the attached two figures for Avalon ST ip for p tile and h tile .

And also please note that , we do not have any app note or reference design for the migration 

Tags (1)
Rahul_S_Intel1
Employee
253 Views

p tile and h tile 

FeatureGNchiP
Employee
246 Views

Hi,

  Actually, the attached waveforms are the reference to start the separate logic for migration activity. what am trying to do using separate logic means, separate the header information from pcie_rx_st_data and drives this header information into application app_rx_st_hdr signal and remaining data information into app_rx_st_data signal. 

  Am in wrong direction? 

  What the separate logic need to do, to migrate Ptile to Htile PCIe.

Thanks! 

 

 

Rahul_S_Intel1
Employee
226 Views

Hi,

 I do not have a solid example design or an App note for the migration.

Regards,

Rahul S

FeatureGNchiP
Employee
222 Views

Hi,

    The Glue logic update is done to handle the Htile header information and verified in the lab.

Thanks,

Velmurugan B

  

Reply