Q10.1, cyclone IV and DDR2 altmemphy problem

[Altera_Forum]

Hello, 

I am trying to compile a ddr2 controller using altmemphy as a NIOS peripheral, that is SOPC and avalon bus not stand-alone.  It appears I generated the SOPC feature correctly. I also ran the TCL files as directed but when I try to compile I get the errors below.  Looking at each of the errors, I find that the compiler is complaining about constraints that the TCL files wrote! That is, the assignment editor contains exactly what the TCL file intended.  I have searched the site and can't find any other reference to this problem so I know I am doing something wrong but I don't know what it is.  This is the first time I have tried to compile ddr2 (altmemphy) with Cyclone IV, but use it regularly with Cyclone III and stratix IV. Is there a difference?   Any references I can look at? ( I have already gone through the standard SOPC and User's guide stuff without finding anything that helps)    Error: altmemphy pin placement was unsuccessful  Error: The DQ group with DQS pin "mem_dqs_to_and_from_the_altmemddr[0]" has invalid DQ group assignments  Error: The "2.5 V" I/O standard and/or the "Default" current strength on the pin "mem_dq_to_and_from_the_altmemddr[0]" is not supported for DDR/DDR2 external memory interfaces  Info: The combination of the I/O standard "SSTL-2 Class I" and the current strength "8mA" is a supported setting  Info: The combination of the I/O standard "SSTL-2 Class I" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "SSTL-2 Class II" and the current strength "16mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class I" and the current strength "8mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class I" and the current strength "10mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class I" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class II" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class II" and the current strength "16mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class I" and the current strength "8mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class I" and the current strength "10mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class I" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class II" and the current strength "16mA" is a supported setting  Error: The "2.5 V" I/O standard and/or the "Default" current strength on the pin "mem_dq_to_and_from_the_altmemddr[1]" is not supported for DDR/DDR2 external memory interfaces   ... it goes on the same way for each of the dq pins and dqs pins

[Altera_Forum]

Hello, 

 Apparently the TCL-script doesn't make the correct assignments, "2.5V" "default" current setting is not suitable for ddr pins..  One cause might be the pin names you used, at least that could be the case for a stand-alone implementation..  The TCL-script assumes standard ddr pin names, for example "mem_cas_n" where "mem_" is a settable prefix. If the toplevel pin names are not equal to this I can imagine it can't make the appropriate pin assignments..  Hope that helps!   Grtz, Olaf