I am planning on using the QDRII+ UniPHY ip in Qsys for my Stratix V system. However I would like to be able to make a modification to it, specifically to phase shift the afi_half_clk signal which by the looks of things is unused within the IP core and is there only for convenience. Basically the plan is to run the memory at 320MHz, set the core to half rate so that the afi_clk is running at 160MHz (giving me a 72bit wide interface). As well as that I then need a clock which is half the frequency again (80MHz), but which is shifted by 90 degrees - such that the falling edge of 160MHz clock occurs during transitions of the 80MHz clock. By default the afi_half_clk has a 0 degree phase shift. I can see that after generating the QSYS system I can edit the phase shift of the pll by modifying the generated hdl file (parameter AFI_HALF_CLK_PHASE = "0 ps";). But each time I generate the system again I have to modify the file. Is there a way of making this change using something like a tcl script? Alternatively, I could disable the afi_half_clk output and add my own pll, but would I be able to ensure that it is correctly aligned with the afi_clk? Perhaps if I use the same reference clock for my pll? or would it be better to use the generated 160MHz clock as the reference for the pll? Also, the 80MHz clock has to be 50% duty cycle so using a clock enable to slow the 160MHz clock down is not an option.