We changed our focus from CycloneV to Arria10, so using quartus17. If we use the Altera IP blocks in our previous projects(with Quartus 14), there is not any problem about their simulation models. But after migrated to Q17 with A10 family, we have struggled some problems with the IP models. For example, IP generator creates a simulation model for you on some platforms like Questa. You can use its "msim_setup.tcl" and its compile order directly and the top module of the IP. If you are a designer, you can copy the IP's top module into your project with an entity including a component.
However, while using Arria10 family PLDs, you could not do this. Questa gives an error like "out of bound". After we investigated this issue, the differencies have been found the versions. Whereas the generated top module does not include the "ip_top_name_pkg.vhd" file in "sim" folder, It is generated into "synth" folder. So, your design can be synthesized but its simulation model does not work because of this issue. So, although .tcl file doesn't include the related package compiling process, you have to compile this folder in your -work directory.
Is there any known issue about this problem? We spent a lot of time to solve this problem.
I will be able to give an example with the name of IP and its folders, If it is confusing.
As far as I know, generating IPs for Arria 10 should give you this "sim" folder.
Just to make sure that we are talking about the same thing: if I generate a FIFO ip (named altfifo), I get the following structure:
│ ├── sim
│ │ └── altfifo_fifo_170_v2kp7oa.v
│ └── synth
│ └── altfifo_fifo_170_v2kp7oa.v
│ ├── aldec
│ │ └── rivierapro_setup.tcl
│ ├── altfifo.v
│ ├── cadence
│ │ ├── cds.lib
│ │ ├── cds_libs
│ │ │ ├── altfifo.cds.lib
│ │ │ └── fifo_170.cds.lib
│ │ ├── hdl.var
│ │ └── ncsim_setup.sh
│ ├── mentor
│ │ └── msim_setup.tcl
│ └── synopsys
│ ├── vcs
│ │ └── vcs_setup.sh
│ └── vcsmx
│ ├── synopsys_sim.setup
│ └── vcsmx_setup.sh
Don't you get this kind of directories? There is the sim/mentor/msim_setup.tcl file that you mentioned.
If not, did you check the select "create simulation model" when generating the IP?
Last thing, can you copy the error message from Questa?
Just wanted to check with you, based on few suggestion provided to your following query, is your concern has been addressed?
If yes, kindly do let me know.
We do not receive any response from you to the previous answer that have provided. This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts.
Otherwise, the community users will continue to help you on this thread.