Hello
I have problems compiling an unofficial reference project for the Arria II GX FPGA Development Kit (http: // www .
altera.com/products/devkits/altera/kit-aiigx-pcie.html).
The project contains an Nios 2 processor and some peripheral components like the DDR3 controller and triple speed ethernet MAC.
Since there are no ethernet reference projects for this kit, i use the Nios II Ethernet Standard Design Example (http: // www .
altera.com/support/examples/nios2/exm-net-std-de.html). It supports Cyclone III and Stratix IV.
From http: // www .
nioswiki.com/ExampleDesigns/Nios_II_Ethernet_Standard_RGMII_Design_Example i get an modified version which work for the Arria II GX and uses the RGMII interface my kit is supposed to use.
The problem is this design is targeted to Quartus II v9.1 and i use v10. The design compiles fine in 9.1 but there is a bunch of new problems with that. The RGMII software support in 9.1 for example.
So when i compile in v10 i get the following message:
Critical Warning: DDR Timing requirements not met
TimeQuest shows that the problem is in Read Capture:
Info: Address Command (Slow 900mV 85C Model) | 1.480 0.803
Info: Half Rate Address/Command (Slow 900mV 85C Model) | 4.778 0.738
Info: Phy (Slow 900mV 85C Model) | 0.647 0.230
Info: Phy Reset (Slow 900mV 85C Model) | 0.749 0.493
Warning: Read Capture (Slow 900mV 85C Model) | -0.010 0.577
Info: Read Resync (All Conditions) | 0.638 0.779
Info: Write (Slow 900mV 85C Model) | 0.232 0.317
Do anyone have an advice of what is should do to remedy this problem. I have tried changing clock frequencies but the 300 MHz is use now is as low as i can go.
I have attached the whole timequest report + two extracts of it where the timing fails.
Any help would be appreciated.
Regards
Christian S.
