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Quartus Prime v18.1 : Arria 10 DDR4 Controller & PHY

bjwinter
Beginner
132 Views

This error appears when I attempt to Synthesize a design containing a DDR4 Controller and PHY combination in an Arria 10 target.

Error (129029): Input port RZQIN on atom "ddr4:u_ddr4|ddr4_altera_emif_181_qumtwji:emif_0|ddr4_altera_emif_arch_nf_181_ebhl3ui:arch|ddr4_altera_emif_arch_nf_181_ebhl3ui_top:arch_inst|altera_emif_arch_nf_oct:oct_inst|cal_oct.powerup_oct_cal.termination_inst", which is a twentynm_termination primitive, is not connected to a valid source

The error indicates an issue with auto-generation of the IP, where the above input is not being driven.

NOTE : I have submitted the error dump via the in application request.

Any assistance on this matter would be greatly appreciated!

 

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2 Replies
AdzimZM_Intel
Employee
117 Views

Hi Bradley,


Thanks for using Intel Community.


I will assist you on this topic.


Regards,

Adzim



AdzimZM_Intel
Employee
109 Views

Hi Bradley,

 

You need to make a connection in your top level design for the instances.

  • OCT
  • Reset

 

The EMIF_pll_ref_clk cannot be hooked up to internal PLL pin.

It's must be connected to external pin.

 

There are several dq pins that are not fit in the design.

So I let the Quartus to Auto Fit the signals pin location.

 

I will share the design that I've edited.

I hope it's working just like you wish.

 

Thanks,

Adzim

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