I've been struggling with a design using a fifo and think I found a bug in the synthesizer. I'm using a very small single clock fifo (8*2 bits) instantiated many times in a component. As it wasn't working I started to put signaltap probes and soon realized that the fifo was always reporting empty=1 even when I was writing to it. After further investigation I found out that the usedw vector is updated correctly when I write to it, it's just the empty signal that is wrong.I managed to reproduce the problem in a very simple project with only the fifo instantiation. My project is with an EP4CE75F23I7 and here is the code (top level):
library ieee; use ieee.std_logic_1164.all; library altera_mf; use altera_mf.altera_mf_components.all; entity testfifo is port ( aclr : in std_logic ; clock : in std_logic ; data : in std_logic_vector (1 downto 0); rdreq : in std_logic ; empty : out std_logic ; q : out std_logic_vector (1 downto 0); wrreq : in std_logic ); end entity testfifo; architecture RTL of testfifo is begin FifoInst : scfifo generic map ( add_ram_output_register => "OFF", intended_device_family => "Cyclone IV E", lpm_numwords => 8, lpm_showahead => "ON", lpm_type => "scfifo", lpm_width => 2, lpm_widthu => 3, overflow_checking => "ON", underflow_checking => "ON", use_eab => "OFF" ) port map ( aclr => aclr, clock => clock, data => data, rdreq => rdreq, wrreq => wrreq, empty => empty, q => q ); end RTL;When I look into the RTL viewer inside the 'a_fefifo:fifo_state' entity that generates the full and empty signals, I get the picture shown in attachment. No wonder I don't see any change in my empty signals :D I haven't seen any warning about optimizing things away, and the FIFO works as intended when I set use_eab to "ON" so it really looks like a bug. Can anyone reproduce this? I'd like to be sure it's nothing wrong with my installation before I file a SR. I'm using Quartus II 11.1 SP2 64 bits (subscription edition). Putting use_eab to "ON" isn't a solution for me because I'm already low on M9K blocks in my design. Besides I don't like the idea of using a 9kbits block to hold 16 bits ;) If I don't find a quick solution to this I'll either write my own fifo or use the usedw vector instead of the empty signal to detect if the fifo has any data. Thanks!
Hello,full and empty are also coming from nowhere in previous Quartus versions, e.g, my V9.1 working version with Cyclone III, if the FIFO is implemented in logic cells. It seems to be a pretty old bug - or undocumented limitation. Regards, Frank
I filed an SR and it turns out there were two unrelated problems.First, the RTL view is wrong. With the above project, if you have a look at the technology map viewer, you will see that the logic that generates the empty and full signals is in fact generated, and if you run the FPGA you will see that the FIFO runs correctly. So it looks like the RTL viewer can't always be trusted. As for my FIFO problem, I still don't know what is causing it. But when I tried to copy the project to simplify it and send an archive to Altera, I realized that it worked fine again. It turns out that deleting the db folder solves the problem, and now it works fine with both use_eab to ON or OFF. There must be something in my db that causes a bad optimisation when I put the use_eab to OFF... Anyway, problem solved, even if I still don't know the cause.
--- Quote Start --- So it looks like the RTL viewer can't always be trusted. --- Quote End --- I confess to be surprized, It seems like I have to correct my naive view on the RTL netlist viewer. Good to know. Regards, Frank
I forgot to post a follow-up on this, but after putting an SR with Altera they agreed there was a problem in the RTL viewer and said it would be fixed in a later version.I always assumed that the RTL viewer showed exactly the state of the design between the Analysis and Synthesis and the Fitter steps, but in fact it looks like Quartus is taking some short cuts with some internal IP's. It's good to know!