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Altera_Forum
Honored Contributor I
802 Views

Quatus 10.1 Exception on Deinterlacer Elaboration

Hi, 

 

I have a fairly complex SOPC system which includes a motion adaptive deinterlacer. The SOPC system generates without errors, but when I compile the project, I get the following exception: 

 

Error: IP Generator Error: Exception during elaboration of alt_tapped_delay: java.lang.NullPointerException 

Error: IP Generator Error: Please forward the complete log file (including the following stack trace) with your bug report: 

Error: IP Generator Error: com.altera.etc.tta.fulib.AltTappedDelayInstance.layoutMemories(AltTappedDelayInstance.java:563) 

Error: IP Generator Error: com.altera.etc.tta.fulib.AltTappedDelayInstance.generateStaticTapLengthInstance(AltTappedDelayInstance.java:1118) 

Error: IP Generator Error: com.altera.etc.tta.fulib.AltTappedDelayInstance.generate(AltTappedDelayInstance.java:978) 

Error: IP Generator Error: com.altera.etc.genericentity.ModuleImpl$FileSetProxy.generate(ModuleImpl.java:99) 

Error: IP Generator Error: com.altera.entity.gen.Elaborator.elaborateInternal(Elaborator.java:281) 

Error: IP Generator Error: com.altera.entity.gen.Elaborator.elaborate(Elaborator.java:170) 

Error: IP Generator Error: com.altera.entity.gen.QuartusSynthLink.elaborate(QuartusSynthLink.java:359) 

Error: IP Generator Error: com.altera.entity.gen.QuartusSynthLink.elaborate(QuartusSynthLink.java:342) 

Error: IP Generator Error: com.altera.entity.gen.main.ElaborateCommand.runCommand(ElaborateCommand.java:22) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.processCommandsInternal(JvgenQuartusMain.java:340) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.processCommandStream(JvgenQuartusMain.java:244) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.runApp(JvgenQuartusMain.java:189) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.main(JvgenQuartusMain.java:95) 

Error: Can't elaborate user hierarchy "OSD:OSD_Inst|DeInterlacer:the_DeInterlacer" 

 

I am using Quartus 10.1SP1 and I am targeting the EP4CE40F23C6 device. I have compiled the system for the Cyclone 3, also using Quartus 10.1, without any problems. Has anybody seen something like this or know how I can get past it? I guess I have to go to Altera Support with this... 

 

Regards, 

Niki
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4 Replies
Altera_Forum
Honored Contributor I
40 Views

you might try 10.1sp1 to see if someone has caught the issue before you, or else file a Service Request

Altera_Forum
Honored Contributor I
40 Views

Hi, 

 

I forgot to mention that I am already using 10.1SP1. I did file a service request.  

 

I actually need to get an urgent, accurate resource usage for the Cyclone IV device. I need to decide between a C40 and C55, which has a significant cost impact. The Cyclone III and IV are so nearly identical that I guess I could use the CIII results. Final product will have to be on a CIV, so I do need to get the problem fixed at some point.  

 

Anyway, not much I can do but wait for an answer from Altera. 

Regards, 

Niki
Altera_Forum
Honored Contributor I
40 Views

you should explain that point in your SR 

 

i agree that you should get a pretty clear picture from a CIII resource count and then verify whether a 4C40 will work or not
Altera_Forum
Honored Contributor I
40 Views

Hi, 

 

I got a response from Altera that it is a known issue for CIV and Stratix V. It will be fixed in the next release. Hope it is not too long from now... 

 

Regards, 

Niki
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