Questasim Error vsim-3043/vsim-3986

[Apaul1]

Hi,

I am facing the below questasim simulation  error. Could you please help me on it... The full log file is attached in this ticket..

# ** Error: (vsim-3043) Unresolved reference to 'alt_eth_25g'.
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles File: ../compilation_test_design/support_logic/alt_eth_25g_auto_tiles.sv Line: 1376
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_tx_NIOS_pause_request'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(118).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_rx_NIOS_pause_request'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(120).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_lphy_signal_ok'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(143).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_pld_adapter_tx_pld_rst_n'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(145).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_pld_tx_dll_lock_req'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(147).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_pld_adapter_rx_pld_rst_n'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(149).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_pld_rx_dll_lock_req'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(151).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_pld_ready'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(153).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_tx_reset_sfreeze_xcvrif'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(155).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_rx_reset_sfreeze_xcvrif'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(157).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_sfreeze_2'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(159).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_sfreeze_1'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(161).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_sfreeze_0'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(163).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_ux_rx_sfrz'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(165).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Warning: (vsim-3015) [PCDPC] - Port size (16) does not match connection size (32) for port 'i_dp_sip_iflux_ingress_direct_231'. The port definition is at: ../ex_25g/alt_e25_f_100/sim/intc_gdr_rst_i_synchronizers.v(167).
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__reset_controller/x_f_tile_soft_reset_ctlr_sip_v1/x_ftile_reset/rst_ctrl_sync File: ../ex_25g/alt_e25_f_100/sim/ftile_reset.sv Line: 321
# ** Fatal: (vsim-3986) Unhandled port connection.
# Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/alt_eth_25g_auto_tiles/z1577a_x0_y166_n0__avmm1_8 File: ../ex_25g/alt_e25_f_100/sim/f_tile_soft_reset_ctlr_ip_v1.sv
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run_vsim.do PAUSED at line 40
quit
# End time: 00:02:14 on Jul 19,2022, Elapsed time: 0:43:21
# Errors: 2, Warnings: 15711, Suppressed Errors: 76

[EBERLAZARE_I_Intel]

Hi,

Thanks for the log, I will try to check from my side for any info that might help, I will get back to you.

[Apaul1]

Hi,

Thanks for the response. The error got fixed. It was due to the auto_tiles file instantiated in the tb file. 

Regards,

Alex J Paul

[EBERLAZARE_I_Intel]

Hi,

Thanks for the update, glad your issue is fixed!