Question on 5SGXMA3K3F40C4 DDR3 IP

[LH12]

We implement DDR3 IP on the device and saw some stability issues between FPGAs of the same type. Some FPGA works fine while some is not working even though the same firmware is being used. Would like to understand more about this observation to see how we can create a more stable firmware.

[Rashmi1]

Hello Ling Hong,

What performance issues are you noticing ,can you please elaborate on that?

Thanks,

Rashmi

[YTLim]

Hi Rasmi,

Allow me to elaborate.

In our H/W architecture, we have 2 physical DDR3 modules connected to the FPGA. We implemented the DDR3 IP on the above mentioned FPGA successfully. However we did see some FPGA to FPGA stability issues.

A particular firmware may work on some FPGAs but may fail on another FPGA of the same type. While another firmware with slight tweaks may work on all the FPGA.

Some other very minor firmware tweaks, even if we did not touch the DDR IP, may cause both DDR3 modules to fail on all FPGAs.

One of the key indicator that we look for in the implementation is the ddr_init signal. On some FPGA, we can see a successful init while on some other, the init was unsuccessful. It could happen to one or the other DDR module or both modules.

If both DDR modules are able to be initialized, the whole system will run fine.

Let me know if you require more information.

[Rashmi1]

HI Ling Hong,

I had sent you an email providing the stage 1 for debug steps. Did you get a chance to go over and see if all those parameters are correct ?

I will further debug the reason for init variation .

Thanks,

Rashmi