I read PCIE User Guide(ug_pci_express.pdf) and there are definitions about tx_fifo_rdptr and tx_fifo_wrptr on page 99. From these two signal definition, I kown that the depth of Avalon-ST adapator TX FIFO is 16, Is it 64-bit width?Also I have anther 2 quetions according to Avalon-ST adapator TX FIFO. 1. On TX path does Avalon-ST adapator have only one FIFO which would buffer all types of TLPs (non-posted, posted and completion)? 2. On page 64 of User Guide, there is some introduction as following. If all types of TLPs are buffered in only one TX FIFO of Avalon-ST adaptor, it is complexer for users to judge when the specific type of TLP is poped from this FIFO. Can users only use read and write FIFO pointers to accout for credits pending in the Avalon-ST adaptor? Is these a simple methor to do this while guaranteeing the performance of DAM? (P64: You must account for completion and posted credits which may be pending in the Avalon-ST adapter. You can use the read and write FIFO pointers and the FIFO empty flag to track packets as they are popped from the adaptor FIFO and transferred to the transaction layer. ) Thank you very much.
Hi shsh30. Since I'm no expert, & not sure what might change with different PCIE generation options, how about just monitoring when tx_fifo_wrptr increments when you TX your data in? (look in sim or w/ SignalTap) That should verify whether the width is indeed 64b for your configuration.I think the fifo is used for all types, but again, looking at when tx_fifo_wrptr increments will confirm it for you (when you tx the different types of packets). Let me step back a second & ask: What type of performance requirements do you have? Or what type of traffic pattern are you concerned about? I ask because most folks can probably get all the performance needed while ignoring the fifo depth, rd/wr ptrs, and credits. Hopefully, you'd only need to follow the rules for tx_st_ready backpressure. -Brian