Hello,
I am trying to simulate the RapidioII core generated using the Megawizard in the Quartus 13.0.1 SJ edition by following all the steps in the User Guide. I noticed that there is no simple black box of this core that I can use directly in my testbench so I am trying to use the provided sv testbench. I have not succeeded even though I followed these steps :
1. Go into the modelsim directory where the msim_setup.tcl is, launch the msim_setup (my modelsim : Modelsim Altera Starter Edition 10.1d)
2. Set the TOP_LEVEL_NAME rapidio2.tb_rio (the IP has been created with the name rapidio2
3. ld
4. Add waves..
5. run -all.
Doing this, i can see that the reset goes high after a certain time but the rapidio2 cores, sister and the main one, are stuck at port_initialized ='0', which blocks the simulation. How do i remedy this?
Thank you.
