FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5879 Discussions

[RAPIDIO_II] BIG PROBLEM with Rapidio II Modelsim Simulation TB

Altera_Forum
Honored Contributor II
774 Views

Hello, 

I am trying to simulate the RapidioII core generated using the Megawizard in the Quartus 13.0.1 SJ edition by following all the steps in the User Guide. I noticed that there is no simple black box of this core that I can use directly in my testbench so I am trying to use the provided sv testbench. I have not succeeded even though I followed these steps : 

1. Go into the modelsim directory where the msim_setup.tcl is, launch the msim_setup (my modelsim : Modelsim Altera Starter Edition 10.1d) 

2. Set the TOP_LEVEL_NAME rapidio2.tb_rio (the IP has been created with the name rapidio2 

3. ld 

4. Add waves..  

5. run -all.  

 

Doing this, i can see that the reset goes high after a certain time but the rapidio2 cores, sister and the main one, are stuck at port_initialized ='0', which blocks the simulation. How do i remedy this? 

 

Thank you.
0 Kudos
0 Replies
Reply