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RGMII with the triple speed ethernet MAC core

Altera_Forum
Honored Contributor II
3,336 Views

Hello, 

 

I have a board with a Stratix II 180 C3 FPGA and a Marvell gigabit Ethernet PHY. The MDIO connection with the Phy works well. I can get the Phy status/id/etc. I also receive Ethernet packets with no problem but when I send a packet nothing goes out of the Phy. The link status is ok and I don't have any error. It's just that the packet is not sent. The packet is output from the MAC though (I checked with a scope) 

 

So has anybody used the TSE core with a RGMII interface to the Phy? 

 

Any idea to make this work? Or things I should look at? 

 

I also have a nios dev kit and the 10/100/1000 Phy daughter board. Altera provides an example in GMII mode that works ok and I will modify it to use RGMII an RMGII interface.  

 

Anybody knows where I can get the 10/100/1000 Phy daughter board pin-out? I searched on the Altera web site but found nothing. 

 

Thanks 

 

Marc
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Altera_Forum
Honored Contributor II
249 Views

hi, 

 

I remember that there is register in the MARVELL PHY to control 

the RGMII receive/transmit timing. You can try to see them.  

 

regards,
Altera_Forum
Honored Contributor II
249 Views

 

--- Quote Start ---  

hi, 

 

I remember that there is register in the MARVELL PHY to control 

the RGMII receive/transmit timing. You can try to see them.  

 

regards, 

--- Quote End ---  

 

 

Thanks, that was it. I adjusted the tx clock to data skew and now it works perfectly :) 

 

Marc
Altera_Forum
Honored Contributor II
249 Views

Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now. 

 

Information on setting the timing of RGMII interface 

6.2.1 Receive Direction 

The FPGA can accept clock edge aligned input data by adding pin-delay to the data inputs 

ensuring proper DDR sampling. This can be achieved by applying negative hold-time 

constraints (e.g. -1.5ns) to the data input pins of the FPGA.  

 

If the pin-delay should not be used, alternatively the PHY can be instructed to add delay to its clock output pin by setting bit 7 of the MDIO register 20. To do so, the following procedure should be followed: 

• read register 20 

• set bit 7 to enable rx clock pin output delay preserving all other bits 

• write register 20 

• Issue a software reset to the phy to apply the change, by reading register 0 

(CONTROL) and writing it back with bit 15 (reset) set to 1. 

 

6.2.2 Transmit Direction 

A typical DDR output implementation supporting multiple speeds in RGMII will provide the 

clock edge aligned with the data edge. However, as the board does not implement a board 

trace delay, the clock needs to be shifted by 2ns to ensure proper timing at the PHY device 

inputs. 

This can be done by either implementing a corresponding shift in the FPGA, or by setting the integrated delay transmit option (bit 1) within the MDIO register 20 of the PHY. To set the transmit delay option, the following procedure should be followed. 

• read register 20 

• set bit 1 to enable tx clock pin input delay preserving all other bits  

• write register 20 

• Issue a software reset to the phy to apply the change, by reading register 0 (CONTROL) and writing it back with bit 15 (reset) set to 1.
Altera_Forum
Honored Contributor II
249 Views

Hi, 

 

The Altera Cyclone III 120 dev kit (DK-DEV-3C120N) has the same Marvell 88E1111 PHY hooked up to the FPGA in RGMII mode. It would not transmit until I added a +2ns phase shift on the GTX_CLK signal. I'm using it with the TSE MAC, with a PLL that generates 2 125MHz clocks, one with 0 degree phase going to the TSE tx clk, another with 90 degree phase shift going to the PHY. This board also has no power up or reconfig reset, which the PHY needs. 

 

-Paul
Altera_Forum
Honored Contributor II
249 Views

 

--- Quote Start ---  

Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now. 

 

It seemed 8.0 now support RGMII 10/100 mode now. But do we need to set something to use 10/100 mode? Or just work without do anything. 

 

Thanks,
Altera_Forum
Honored Contributor II
249 Views

how can i read/config registers?

Altera_Forum
Honored Contributor II
249 Views

Hi,  

You can read to a register by using this: 

 

TSE_cmd_reg = IORD_ALTERA_TSEMAC_CMD_CONFIG(TSE_MAC_BASE); 

 

for a write: 

IOWR_ALTERA_TSEMAC_CMD_CONFIG(TSE_MAC_BASE,TSE_cmd_reg); 

 

Jan
Altera_Forum
Honored Contributor II
249 Views

hey guys, has anyone tried to make the TSE work in 100base mode? 

with tse 8.1.  

I'm having problem to do that.
Altera_Forum
Honored Contributor II
249 Views

Hello liangbowen (http://www.alteraforum.com/forum/member.php?u=27864) I made transmition of packet with TSE in 100 mbit mode witj rgmii (q8.1 SP1)

Altera_Forum
Honored Contributor II
249 Views

 

--- Quote Start ---  

Hello liangbowen (http://www.alteraforum.com/forum/member.php?u=27864) I made transmition of packet with TSE in 100 mbit mode witj rgmii (q8.1 SP1) 

--- Quote End ---  

 

 

hi dim, did you encounter any problem? can you guide me to implement that?  

what's the phy chip you are using? 

 

thanks.
Altera_Forum
Honored Contributor II
249 Views

Hello liangbowen, as i see, i also work with TSE and marvell PHY. 

 

Now i have workable transmit part from nios to PC, but i have some problems with receiving of packet. 

So i can help you with transmit and you can help me with receive. 

 

My configuration is: 

Q 8.1 SP1 nios II 8.1 

TSE 

Marvell 88e1111 

 

I send packets from nios through the MAC level and i want to receive it the same way from the PC. 

At first it would be great to now how you made the receive of packet? 

i try to make it by alt_avalon_sgdma_register_callback which will be launched after the packet came to PHY->MAC. 

But i can't make it to step into the isr function in debug mode, i don't know what is the problem... 

 

So i'll answer all your questions.
Altera_Forum
Honored Contributor II
249 Views

Glad to know that you are using the same PHY, but my implementation uses pure verilog. can't help you with nios ii.

Altera_Forum
Honored Contributor II
249 Views

If anyone has problems with the PHY on 3sl150 Stratix III kit, please, check this out: 

http://www.alteraforum.com/forum/showthread.php?p=86569#post86569
Altera_Forum
Honored Contributor II
249 Views

 

--- Quote Start ---  

Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now. 

 

Information on setting the timing of RGMII interface 

6.2.1 Receive Direction 

The FPGA can accept clock edge aligned input data by adding pin-delay to the data inputs 

ensuring proper DDR sampling. This can be achieved by applying negative hold-time 

constraints (e.g. -1.5ns) to the data input pins of the FPGA.  

 

If the pin-delay should not be used, alternatively the PHY can be instructed to add delay to its clock output pin by setting bit 7 of the MDIO register 20. To do so, the following procedure should be followed: 

• read register 20 

• set bit 7 to enable rx clock pin output delay preserving all other bits 

• write register 20 

• Issue a software reset to the phy to apply the change, by reading register 0 

(CONTROL) and writing it back with bit 15 (reset) set to 1. 

 

6.2.2 Transmit Direction 

A typical DDR output implementation supporting multiple speeds in RGMII will provide the 

clock edge aligned with the data edge. However, as the board does not implement a board 

trace delay, the clock needs to be shifted by 2ns to ensure proper timing at the PHY device 

inputs. 

This can be done by either implementing a corresponding shift in the FPGA, or by setting the integrated delay transmit option (bit 1) within the MDIO register 20 of the PHY. To set the transmit delay option, the following procedure should be followed. 

• read register 20 

• set bit 1 to enable tx clock pin input delay preserving all other bits  

• write register 20 

• Issue a software reset to the phy to apply the change, by reading register 0 (CONTROL) and writing it back with bit 15 (reset) set to 1. 

--- Quote End ---  

 

 

Hello, 

 

Can we apply these suggested steps on Cyclone III (C120)?  

 

Thanks
Altera_Forum
Honored Contributor II
249 Views

I'm using the Altera Triple Speed Ethernet IP with cyclone iii, and trying to test the Rx and Tx of 10/100/1000 Ethernet MAC(RGMII). The test is done as following: 

1- setting the loop_ENA bit in command_config register to 1 and  

2-comparing the statistics counters aFramesTransmittedOK and 

aFramesReceivedOK to verify that the transmit and receive frame counts are equal. 

3-checking the statistics counters ifInErrors and ifOutErrors to determine the number of packets transmitted and received with errors. According to the attached file named"Triple Speed Ethernet User Guide" 

So, kindly send me a design example made using the SOPC Builder to perform the internal MAC local loopback on it. 

 

Thanks
Altera_Forum
Honored Contributor II
249 Views

 

--- Quote Start ---  

hi, 

 

I remember that there is register in the MARVELL PHY to control 

the RGMII receive/transmit timing. You can try to see them.  

 

regards, 

--- Quote End ---  

 

 

Hello, 

 

I did not found the detailed datasheet for the MARVELL PHY device, can you send it to me. 

 

Thanks
Altera_Forum
Honored Contributor II
249 Views

 

--- Quote Start ---  

 

I did not found the detailed datasheet for the MARVELL PHY device, can you send it to me. 

 

--- Quote End ---  

 

 

You'll need to contact Marvell and sign an NDA to get a hold of their datasheets.
Altera_Forum
Honored Contributor II
249 Views

can anyone tell me bullet steps for ethernet interface..becoz im new here,and im not getting any idea of how to start..i am working with evalution board-cycloneiii ep3c120f780c7 device and 88e1111 marvell chip on it...

Altera_Forum
Honored Contributor II
249 Views

download the kit update from the Altera website. The standard example includes the Ethernet interface.

Altera_Forum
Honored Contributor II
147 Views

can u please tell me where can i get the document for the reference design for "Niosii_ethernet_standard_3c120_rgmii"

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