RGMII with the triple speed ethernet MAC core

[Altera_Forum]

Hello, 

 I have a board with a Stratix II 180 C3 FPGA and a Marvell gigabit Ethernet PHY. The MDIO connection with the Phy works well. I can get the Phy status/id/etc. I also receive Ethernet packets with no problem but when I send a packet nothing goes out of the Phy. The link status is ok and I don't have any error. It's just that the packet is not sent. The packet is output from the MAC though (I checked with a scope)  So has anybody used the TSE core with a RGMII interface to the Phy?  Any idea to make this work? Or things I should look at?  I also have a nios dev kit and the 10/100/1000 Phy daughter board. Altera provides an example in GMII mode that works ok and I will modify it to use RGMII an RMGII interface.   Anybody knows where I can get the 10/100/1000 Phy daughter board pin-out? I searched on the Altera web site but found nothing.  Thanks  Marc

[Altera_Forum]

here (ftp://ftp.altera.com/outgoing/devkit/cycloneiii_3c120_dev_kit-v9.0.2.exe). But the project name is "cycloneIII_3c120_dev_niosII_standard".

[Altera_Forum]

hi,thank u very much for ur reply,& thanks for the files,but what actually i need is pdf documentation file explainig the reference design of niosii ethernet standard.. example,why because here iam new to verilog and cycloneiii,i need a quick explanation of working of that ref design..,i am having cycloneiii ep3c120f780c7,and i need to access ethernet interface by using tse ip core..so can u guide me where can i start,& wher to refer, 

 thank u very much for ur response..

[Altera_Forum]

The only documentation I know of is the TSE datasheet. The design example then shows you how it can be connected on the Cyclone III development kit. 

If you are new to Verilog, it could be a good idea to try some simpler tutorials about the language and FPGAs first, because setting up an Ethernet interface in an FPGA isn't an easy task for a beginner, unfortunately.

[Altera_Forum]

hai  

can u help me to bring up rgmii on arriaiigx board .... im not using tse mac core ,im using my own core for rgmii ...my core is working for 100mbps but it is not working for 1g in rgmii mode   reply as soon as possible

[Altera_Forum]

I only have experience with the TSE core, I never tried to generate my own rgmii signals.

[Altera_Forum]

--- Quote Start ---  Thanks, that was it. I adjusted the tx clock to data skew and now it works perfectly :)  Marc  --- Quote End ---    Seems to be the same problem for me.  How did you set up the register? Through the MAC or directly by the MDIO signals?  I dont have the datasheet for the Marvell PHY. Is it possible for you to tell me exactly how to set it up?  Thanks

[Altera_Forum]

I had the same problems: 

Terasic DE2 Evaluation Board with Marvel 88E1111: I use the TSE-Core from Altera, connected over RGMII.  I do no special setup of the Marvel Chip, because I also have no datasheet.  The hint with the 90deg phase was the solution. I created a PLL for the 125 MHz signal. The 0-degree frequency goes into the TX_clock of the IP-core. The 90-degree freqency goes into the PHY GTX clock.  Then sending of a frame succeeds.

[Altera_Forum]

--- Quote Start ---  I do no special setup of the Marvel Chip, because I also have no datasheet.  The hint with the 90deg phase was the solution. I created a PLL for the 125 MHz signal. The 0-degree frequency goes into the TX_clock of the IP-core. The 90-degree freqency goes into the PHY GTX clock.  Then sending of a frame succeeds.  --- Quote End ---    Does this work for non-gigabit speeds? My PHY is running at 100Mb and I am confused whether the clock needs to be delayed 90deg or a fixed amount of time. Big difference when switching between 125, 25, and 2.5MHz. Ideally I would like the ethernet port to handle all three link speeds.  I am trying to get RGMII working on the arria ii devkit, and maybe this is my problem. I've also seen discussion of writing to a register in the PHY to let it handle the clock skew, but I have not seen and code to actually do this.  Any insight into this matter will be appreciated.

[Altera_Forum]

>> Does this work for non-gigabit speeds? 

 No, my solution was only for GBit-Ethernet, because my application needs that speed. I ignored 100MBit and lower.  Because I don't have a datasheet, I do not know anathing about the special registers of the marvel chip. The regular registers of most PHYs are described in the Xilinx document Ug194.pdf , Chapter 5, MDIO Interface. ( The system does not allow me to post the link here)