RX BITSLIP in E-Tile XCVR PHY Gearbox 64/66 mode

[LNagy2]

Hello community, 

I would be interested on more details on the RX BITSLIP  used in  "Gearbox 64/66" mode in the E-Tile XCVR PHY IP.

I did not find any timing information for the rx_pmaif_bitslip port of the IP. 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_etile_xcvr_phy.pdf

Based on simulations I found that for a lane rate of 16.5Gpbs ,

it must be asserted until the rx_parallel_data[70] bit is set,

wait another 64 cycles until next assertion. 

Is there a general explanation for the bit slip timing behavior/requirements ? 

Thank you, 

Laszlo