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Read/Write EMIF DDR4

Rleduc
New Contributor I
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Hello,

 

I'm working on Arria 10, trying to read and write data to external memory DDR4.

 

Write part :

My data comes out from a FIFO and is 16 bits wide. I need to implement a logic that can read N times from FIFO and write in DDR4 memory, which means through avalon-mm interface.

 

Since DDR4 writedata (and readdata) is 256 bit wide, "avalon-write IP" that I would implement would take 8 samples of FIFO data (8x32=256) and then write this whole 256b vector to the EMIF avalon-mm.

 

Read part :

 

For reading data stored in DDR4 from HPS, I can directly do it with alt_read_word() function and accessing it through avalon-mm bridge and H2F AXI bridge.

 

Issue:

I can read properly what I write in DDR4 from HPS, so this part is not of an issue. However for now, I properly read junk data, because my writing logic is wrong.

From what I understood, EMIF amm uses burst mode. A burstcount of 4 would mean writing 4 times 256b of data, which also means in my case 4x8=32 samples that came from FIFO.

If user asks for 100 samples, I feel like it will be a mess, since I can only work with a fixed number of burst (4,8,16,...1024), whose each is a fixed number of 8 samples. How do I manage the number of bursts that will in the end not exactly be related to the number of samples ? What would be the general logic ? 

Thanks

 

 

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AdzimZM_Intel
Employee
888 Views

Hello,


Maybe you can make a repetitive data to continue provide data during the write or provide "0" after 100 sample.



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Rleduc
New Contributor I
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Hi, thank you for you answer,

I did as you mention, provide 0 data in the last burst which is not full.

 

Now the logic seems good, but I have the following issue :

 

master_write_data[255:0] is properly filled with fifo data, I can see it in signaltap. However the EMIF amm_write_data[255:0] (slave) which is directly connected to master_write_data[255:0] is equal to 0x0 ! I don't understand how is this possible, is it supposed to be the same net ?

For information, local calibartion is in success, no reset. The only thing that I can notice is that :

- waitrequest_n is always 0, so I can wait forever

- I am not sure if emif clock which is 266MHz on the DDR4 side should be the same as fifo clock which is for now 100 MHz,. Should I use the clk output from emif "usr_clk" as well as "usr_reset" to feed the fifo ? Can clock cross domain work ?

 

Thanks !

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AdzimZM_Intel
Employee
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Hi,


I think you may try to read back the data that you have wrote in the memory.

Because not all signals can be read through the SignalTap.


Usually the usr_clk and usr_reset with be fed to traffic generator or user logic.

I think the fifo should be working fine if you fed with this signals.


Regards,

Adzim


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AdzimZM_Intel
Employee
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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