Hi all, I am using the sopc builder sram core to operate an asram under a tri-state bridge.I wonder if it is possible to complete a read operation in one clock period, which is associated with the tri-state bridge. I have tried to set the parameter as following: Set up time: 0 cycle; Read wait time:0 cycle; Read latency: 1 cycle; Assert chip select through readlatency: enabled. With these settings, I can read a data in 1 cycle, but errors data may happen.
Which SRAM are you using? What are the timing requirements for that SRAM part? The part's setup and hold requirements, along with your clock frequency will determine how many cycles are required to read the SRAM.Jake
Thanks for your reply. I think I have gotten the key by constraining the timing.
I used the ISSI102416 and my system clock is 100MHz. The device has a maxium access time of 10ns. Namely, the data will be available 10ns after it's address is valid.
At first, I used two cycles to read data from the sram, the first cycle for output address and the other for get data. This method works of course, but the cost is that the access time is reduced to 20ns.
The document "Async RAM Example.doc" helps me a lot. According to the example, I constrains the input delay of sram data signals and finnally achieves my goal. My settings for the sram core are just as follows:
Set uptime: 0 cycle.
Read wait time: 0 cycle.
No read latency.
Hope this would help someone else who may meet the same problelm as mine.