Did calibration complete properly on the memory? What type of memory? I've seen it where the write is still pending and cannot complete since the memory is not available (failed calibration) so the reads get held up. Also note that readdatavalid only occurs when you are reading bursts (I think), and if it's just one read then the waitrequest indicates when read data is valid.
Is it possible you are asserting too many addresses to read from? From what I'm seeing the waitrequest signal is high most of the time. When asserted, this signal forces the host to wait until the interconnect is ready to proceed with the transfer. At the start of all transfers, a host initiates the transfer and waits until waitrequest is deasserted. This waitrequest delays the read/write process.
You may find this video helpful: https://www.youtube.com/watch?v=8GAqT3nzHeQ
More information about the signals used and burst transfers here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
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