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Altera_Forum
Honored Contributor I
1,000 Views

Recovery violations uniphy DDR3

hi,  

 

I Have 3 external DDR3 64-bt interfaces at 500 MHz in a stratix iv, they are setup as one master and 2 slaves, sharing one PLL and a DLL.  

 

Timing is good except for recovery violations (BIG -1.4 ns) on some reset path inside the uniphy core.  

As anyone experienced that problem and found a solution? 

 

thank you,  

 

IT
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Altera_Forum
Honored Contributor I
136 Views

This issue is described in the MegaCore IP Library Release Notes and Errata as "Reset Synchronizer May Cause Design to Fail Timing". 

 

You can set on the paths to avoid timing failure: 

set_false_path -from *:rst_controller*|*:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out -to *|*:umemphy|*:ureset|*:ureset_*_clk|reset_reg
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