FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6355 Discussions

Reduce the DDR clock below 300 MHz

Moti
Employee
644 Views

Hi

 

I use Quartus 20.3 pro for Stratix10 FPGA, DDR3 1600.

need to config clock below 300MHz  at the IP.

at the DDR datasheet I found that I can run it slower.

I have attached the error I received, is it possible to configure the IP to support slower clock?

 

Thanks.

Moti

 

 

 

0 Kudos
1 Solution
Deshi_Intel
Moderator
613 Views

HI,


Yup, as you can see from your own error screenshot, it's not supported.


Thanks.


Regards,

dlim


View solution in original post

3 Replies
sstrell
Honored Contributor III
629 Views

Are you saying you want to drive the external memory at a lower speed or run the internal logic at a lower speed?  The internal logic runs, based on your current setting, at 1/4 the speed (quarter rate mode) of the external memory clock.  If you're saying you want to run the external memory at a lower speed, then you can't, as the message indicates.

Deshi_Intel
Moderator
614 Views

HI,


Yup, as you can see from your own error screenshot, it's not supported.


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
591 Views

You are welcome !


0 Kudos
Reply