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tessellation
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Reed Solomon II IP ModelSim TCL not able to compile

Hi,

I have made a project containing a simple test bench for the Reed Solomon II IP core Encoder and Decoder. I have used the TCL generated by Quartus (Generate Simulator Setup Script) and edited it to include my other project files as per usual for simulation in ModelSim. However, the compiler exits after some suppressible errors. Please see below all messages from ModelSim. Hence I cannot use the Reed Solomon II IP core.

 

# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with  -voptargs=+acc
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
# 
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
# [exec] dev_com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:02:58 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSencoder/rs_encoder/altera_rs_ser_enc_191/sim/rs_encoder_altera_rs_ser_enc_191_ykixe2y.vhd -work altera_rs_ser_enc_191 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_encoder_altera_rs_ser_enc_191_ykixe2y
# -- Compiling architecture rtl of rs_encoder_altera_rs_ser_enc_191_ykixe2y
# End time: 11:02:58 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:02:58 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSencoder/rs_encoder/altera_rs_ser_enc_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_enc_191 
# 
# Top level modules:
# End time: 11:02:58 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:02:58 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSencoder/rs_encoder/altera_rs_ser_enc_191/sim/mentor/altera_rs_ser_enc.sv -work altera_rs_ser_enc_191 
# 
# Top level modules:
# End time: 11:02:59 on Aug 24,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:02:59 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSencoder/rs_encoder/altera_rs_ii_191/sim/rs_encoder_altera_rs_ii_191_cnsuyai.vhd -work altera_rs_ii_191 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_encoder_altera_rs_ii_191_cnsuyai
# -- Compiling architecture rtl of rs_encoder_altera_rs_ii_191_cnsuyai
# -- Loading entity rs_encoder_altera_rs_ser_enc_191_ykixe2y
# End time: 11:02:59 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:02:59 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSencoder/rs_encoder/sim/rs_encoder.vhd -work rs_encoder 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_encoder
# -- Compiling architecture rtl of rs_encoder
# -- Loading entity rs_encoder_altera_rs_ii_191_cnsuyai
# End time: 11:02:59 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:00 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_transaction_converter_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_transaction_converter_191 
# 
# Top level modules:
# End time: 11:03:00 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:01 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_transaction_converter_191/sim/mentor/altera_rs_ser_transaction_converter.sv -work altera_rs_ser_transaction_converter_191 
# 
# Top level modules:
# End time: 11:03:01 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:01 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/data_format_adapter_1920/sim/rs_decoder_data_format_adapter_1920_fkx5dvq.sv -work data_format_adapter_1920 
# -- Compiling module rs_decoder_data_format_adapter_1920_fkx5dvq
# 
# Top level modules:
# 	rs_decoder_data_format_adapter_1920_fkx5dvq
# End time: 11:03:01 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:01 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_avalon_st_splitter_1920/sim/altera_avalon_st_splitter.sv -work altera_avalon_st_splitter_1920 
# -- Compiling module altera_avalon_st_splitter
# 
# Top level modules:
# 	altera_avalon_st_splitter
# End time: 11:03:02 on Aug 24,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:02 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/data_format_adapter_1920/sim/rs_decoder_data_format_adapter_1920_bd66v5a.sv -work data_format_adapter_1920 
# -- Compiling module rs_decoder_data_format_adapter_1920_bd66v5a
# 
# Top level modules:
# 	rs_decoder_data_format_adapter_1920_bd66v5a
# End time: 11:03:02 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:02 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_transaction_format_adapter_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_transaction_format_adapter_191 
# 
# Top level modules:
# End time: 11:03:03 on Aug 24,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:03 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_transaction_format_adapter_191/sim/mentor/altera_rs_ser_transaction_format_adapter.sv -work altera_rs_ser_transaction_format_adapter_191 
# 
# Top level modules:
# End time: 11:03:03 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:03 on Aug 24,2020
# vlog -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_avalon_sc_fifo_1920/sim/rs_decoder_altera_avalon_sc_fifo_1920_thtihqa.v -work altera_avalon_sc_fifo_1920 
# -- Compiling module rs_decoder_altera_avalon_sc_fifo_1920_thtihqa
# 
# Top level modules:
# 	rs_decoder_altera_avalon_sc_fifo_1920_thtihqa
# End time: 11:03:03 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:04 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_syn_191/sim/rs_decoder_altera_rs_ser_syn_191_nmdltnq.vhd -work altera_rs_ser_syn_191 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_decoder_altera_rs_ser_syn_191_nmdltnq
# -- Compiling architecture rtl of rs_decoder_altera_rs_ser_syn_191_nmdltnq
# End time: 11:03:04 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:04 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_syn_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_syn_191 
# 
# Top level modules:
# End time: 11:03:04 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:04 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_syn_191/sim/mentor/altera_rs_ser_syn.sv -work altera_rs_ser_syn_191 
# 
# Top level modules:
# End time: 11:03:05 on Aug 24,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:05 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_bm_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_bm_191 
# 
# Top level modules:
# End time: 11:03:05 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:05 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_bm_191/sim/mentor/altera_rs_ser_bm.sv -work altera_rs_ser_bm_191 
# 
# Top level modules:
# End time: 11:03:05 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:06 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_bm_191/sim/rs_decoder_altera_rs_ser_bm_191_f4ic2cq.vhd -work altera_rs_ser_bm_191 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_decoder_altera_rs_ser_bm_191_f4ic2cq
# -- Compiling architecture rtl of rs_decoder_altera_rs_ser_bm_191_f4ic2cq
# End time: 11:03:06 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:06 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_search_191/sim/rs_decoder_altera_rs_ser_search_191_4xnuspa.vhd -work altera_rs_ser_search_191 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_decoder_altera_rs_ser_search_191_4xnuspa
# -- Compiling architecture rtl of rs_decoder_altera_rs_ser_search_191_4xnuspa
# End time: 11:03:06 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:06 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_search_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_search_191 
# 
# Top level modules:
# End time: 11:03:07 on Aug 24,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:07 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_search_191/sim/mentor/altera_rs_ser_search.sv -work altera_rs_ser_search_191 
# 
# Top level modules:
# End time: 11:03:07 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:07 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_correct_191/sim/mentor/altera_rs_ii_pkg.sv -work altera_rs_ser_correct_191 
# 
# Top level modules:
# End time: 11:03:07 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:08 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_correct_191/sim/mentor/altera_rs_ser_correct.sv -work altera_rs_ser_correct_191 
# 
# Top level modules:
# End time: 11:03:08 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:08 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/data_format_adapter_1920/sim/rs_decoder_data_format_adapter_1920_ksxfhha.sv -work data_format_adapter_1920 
# -- Compiling module rs_decoder_data_format_adapter_1920_ksxfhha
# 
# Top level modules:
# 	rs_decoder_data_format_adapter_1920_ksxfhha
# End time: 11:03:08 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:08 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_avalon_st_adapter_1920/sim/rs_decoder_altera_avalon_st_adapter_1920_v3ukfry.vhd -work altera_avalon_st_adapter_1920 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_decoder_altera_avalon_st_adapter_1920_v3ukfry
# -- Compiling architecture rtl of rs_decoder_altera_avalon_st_adapter_1920_v3ukfry
# -- Loading package vl_types
# -- Loading entity rs_decoder_data_format_adapter_1920_ksxfhha
# End time: 11:03:09 on Aug 24,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:09 on Aug 24,2020
# vlog -reportprogress 300 -sv C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/data_format_adapter_1920/sim/rs_decoder_data_format_adapter_1920_pw4k62a.sv -work data_format_adapter_1920 
# -- Compiling module rs_decoder_data_format_adapter_1920_pw4k62a
# 
# Top level modules:
# 	rs_decoder_data_format_adapter_1920_pw4k62a
# End time: 11:03:09 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:09 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_avalon_st_adapter_1920/sim/rs_decoder_altera_avalon_st_adapter_1920_2ycmx2a.vhd -work altera_avalon_st_adapter_1920 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_decoder_altera_avalon_st_adapter_1920_2ycmx2a
# -- Compiling architecture rtl of rs_decoder_altera_avalon_st_adapter_1920_2ycmx2a
# -- Loading package vl_types
# -- Loading entity rs_decoder_data_format_adapter_1920_pw4k62a
# End time: 11:03:09 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1_3 Compiler 2020.04 Apr 28 2020
# Start time: 11:03:10 on Aug 24,2020
# vcom -reportprogress 300 C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd -work altera_rs_ser_dec_191 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity rs_decoder_altera_rs_ser_dec_191_y4pqgea
# -- Compiling architecture rtl of rs_decoder_altera_rs_ser_dec_191_y4pqgea
# -- Loading entity rs_decoder_data_format_adapter_1920_fkx5dvq
# -- Loading entity altera_avalon_st_splitter
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "in0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out1_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out2_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out3_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out4_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out5_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out6_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out7_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out8_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out9_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out10_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out11_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out12_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out13_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out14_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# ** Error (suppressible): C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(668): (vcom-1130) Port "out15_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.
# -- Loading entity rs_decoder_data_format_adapter_1920_bd66v5a
# -- Loading entity rs_decoder_altera_avalon_sc_fifo_1920_thtihqa
# -- Loading entity rs_decoder_altera_rs_ser_syn_191_nmdltnq
# -- Loading entity rs_decoder_altera_rs_ser_bm_191_f4ic2cq
# -- Loading entity rs_decoder_altera_rs_ser_search_191_4xnuspa
# -- Loading entity rs_decoder_altera_avalon_st_adapter_1920_v3ukfry
# -- Loading entity rs_decoder_altera_avalon_st_adapter_1920_2ycmx2a
# ** Note: C:/Users/eirene/Documents/Tessa/RS_IPcore/IPcores/RSdecoder/rs_decoder/altera_rs_ser_dec_191/sim/rs_decoder_altera_rs_ser_dec_191_y4pqgea.vhd(1338): VHDL Compiler exiting
# End time: 11:03:10 on Aug 24,2020, Elapsed time: 0:00:00
# Errors: 17, Warnings: 0
# C:/intelFPGA_pro/20.2/modelsim_ase/win32aloem/vcom failed.

 

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