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Reed Solomon IPcore 13.0 problem

Altera_Forum
Honored Contributor I
832 Views

Hello,  

I'm trying to use the evaluation version of the RS encoder and decoder. I configured it as (223,255) with 8bit symbols and cascaded them, generating the control signals with the following module: 

 

module avalon_st_interface( input clk,res, input valid, input data_in, input source_en, output reg sop,eop,source_val, output reg sink_en, output reg data_out, output reg count ); reg valid_mem; always@(posedge clk)begin sink_en<=source_en;end always@(posedge clk)begin data_out<=data_in;end always@(posedge clk)begin valid_mem<=valid;end always@(posedge clk or posedge res) begin if(res) begin count<=9'd0; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end else begin if(!valid_mem & valid & count==9'd0) //first symbol if idle begin count<=9'd1; sop<=1'd1; eop<=1'd0; source_val<=1'd1; end else if(valid & count==9'd222) //next one is the last begin count<=count + 9'd1; sop<=1'd0; eop<=1'd1; source_val<=1'd1; end else if(valid & count==9'd223) //first symbol if keep on transmitting begin count<=9'd1; sop<=1'd1; eop<=1'd0; source_val<=1'd1; end else if(valid & count>=9'd0 & count<=9'd222) //symbols are passing through begin count<=count + 9'd1; sop<=1'd0; eop<=1'd0; source_val<=1'd1; end else if(!valid & count>=9'd0 & count<=9'd222) //interrupted begin count<=count; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end else if(!valid & (count==9'd0 | count==9'd223)) //idle begin count<=9'd0; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end else begin count<=9'd0; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end end end endmodule  

 

Simulations and SignalTap show that sop and eop are generated but I get nothing out of the decoder. I use it with audio data and the output is null, except the source valid signal that is high. Any advice? 

Thank you
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
67 Views

For the encoder your input symbol is 223 words while your output is 255 words. Are you allowing a wait of (255-223 = 32) before new symbol arrives. I can't see that in your code.

Altera_Forum
Honored Contributor I
67 Views

Hi kaz, thank you very much for your reply. 

I forgot myself to include the backpressure control in that code. Now I'm using the sink_enable signal to stop the data stream when the Encoder is not able to receive more data. This way it should be reasonably good, in fact the RS compiler guide says: "By de-asserting sink_ena, the encoder signals that it cannot sink more incoming symbols after sink_eop is signalled at the input. During this time it is generating the check symbols for the current codeword." However it doesn't work, as before. I post the corrected code: 

module avalon_st_interface( input clk,res, input valid, input data_in, input sink_en, output reg sop,eop,source_val, output reg source_en, output reg data_out, output reg count ); reg valid_mem; always@(posedge clk)begin source_en<=sink_en;end always@(posedge clk)begin data_out<=data_in;end always@(posedge clk)begin valid_mem<=valid;end always@(posedge clk or posedge res) begin if(res) begin count<=9'd0; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end else begin if(sink_en) begin if(!valid_mem & valid & count==9'd0) begin count<=9'd1; sop<=1'd1; eop<=1'd0; source_val<=1'd1; end else if(valid & count==9'd222) begin count<=count + 9'd1; sop<=1'd0; eop<=1'd1; source_val<=1'd1; end else if(valid & count==9'd223) begin count<=9'd1; sop<=1'd1; eop<=1'd0; source_val<=1'd1; end else if(valid & count>=9'd0 & count<=9'd222) begin count<=count + 9'd1; sop<=1'd0; eop<=1'd0; source_val<=1'd1; end else if(!valid & count>=9'd0 & count<=9'd222) begin count<=count; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end else if(!valid & (count==9'd0 | count==9'd223)) //idle begin count<=9'd0; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end else begin count<=9'd0; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end end else //backpressure on begin count<=count; sop<=1'd0; eop<=1'd0; source_val<=1'd0; end end end endmodule
Altera_Forum
Honored Contributor I
67 Views

You are still not doing it right. your counter goes from 1 to 223, that is ok but then it becomes 1 and sop of second packet is generated without check on back pressure. 

 

You better run your counter freely on valid from 0 to 254 starting 0 at start of valid. You need to stop your input data and valid at counts 223~255. 

that way you don't need to use back pressure. your sop will be at count 0 & valid while your eop will be at count 222 & vaild.
Altera_Forum
Honored Contributor I
67 Views

Thank you, 

I followed your suggestion and made the symbol burst length equal to 223, in order to avoid backpressure. I use now a simple counter to generate in a deterministic way the control signals. SignalTap shows that things work. I have only one concern: the decoder gives as output (I'm not introducing errors between encoder and decoder) the same word it gets as input, or it doesn't get rid of the redundant symbols. Is that possible? If so, I should write a module that chops those extra symbols...it seems to be weird for a decoder.
Altera_Forum
Honored Contributor I
67 Views

 

--- Quote Start ---  

Thank you, 

I have only one concern: the decoder gives as output (I'm not introducing errors between encoder and decoder) the same word it gets as input, or it doesn't get rid of the redundant symbols. Is that possible? If so, I should write a module that chops those extra symbols...it seems to be weird for a decoder. 

--- Quote End ---  

 

 

It could be that the decoder ejects data and the extra bits but tells you where valid out is. What really matters is does it correct errors. Insert few errors (dispersed) and see.
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