Hi,I am using the Reed Solomon decoder IP core v8.1 and I find the core behaviour a little strange. As long as there are no uncorrectable errors the signals source_val, source_sop and source_eop behave as shown in the user guide and all is well. As soon as there are uncorrectable errors the signals start short-cutting the decoded blocks. As an example when using a (255,239) RS block you would expect the number of clock cycles between the source_sop and source_eop to be 255 and the source_val is active during the entire 255 cycle block. This is the normal behaviour, however when there are uncorrectable errors, the output block length varies depending on where in the RS block the decoder stops correcting errors. This is not mentioned in the user guide. Is this a bug in the IP or the user guide. Hopefully someone has run into this before I did. BR Jens
I'm not completely sure, but the reed solomon core has an unpredictable behavior when the number of error is too high.Anyway when the decoder is correcting an error the source_valid is de-asserted, so it's better to add a ram block or a FIFO past to the RS-decoder to buffer the discontinuities. Marco
excuse me,before asking a difficult thing, which I want to ask: whether reed solomon encoder can be made on Altera FPGA Cyclone IV? how many logicgate are needed to make a reed solomon encoder?