Hello! We are working on an FPGA with the older Avalon OpenCores 10/100 Ethernet MAC (v8.02) which was completed in ~2009 using Quartus 8.x and SOPC builder on a Cyclone III. We have ported the functionality to a new Cyclone IV now using Quartus 13.1 but without converting the SOPC builder component to QSYS.There is an issue currently where after pinging for some period of time (approximately overnight) the Ethernet MAC stops sending the interrupt to the processor for received data packets (only). We can see the TX data going out, the TX interrupt occurs, and the receive data comes back (RXDV is active), however no RX interrupt occurs. Once the FPGA is in this mode, it stays there until it is reset and will never send another RX interrupt until then. 　 1) Has anyone experienced this? 2) Any thoughts on what may be causing it? 3) What would the impact to software be of using the TSE? Is there a Linux driver available? 3) Is it possible to port this from SOPC builder to a QSYS implementation? We would like to use a newer version of the core and see if that fixes it. 8.03 seems to be the newest "stable" version. Jakobjones created a beta version 9.1 sometime in 2010 but it doesn't appear to have ever been finalized based on the searches I've done. Thanks a lot!
I used the Jakobjones's version 9.1 with Quartus 9.0sp2 SOPC and later I migrated it to 11.0 with Qsys.I don't recall about relevant problems, although I'm not sure, since it has been quite a long time so far.
Cris, Thanks for the response. I have it more or less ported to QSYS now, however there is a bug we are trying to work through. For some reason we aren't getting a valid link on the Phy right now. Do you recall if it was 'functional' at all?Thanks much!
Do you mean there's actualy no link, or rather the MAC doesn't get the correct link status from the PHY?In the first case you need to review the PHY initialization. For example I used a PHY which was not included in the jakobjones driver, so I had to add it, although this was not a difficult task.