Regenerating PCIe IP Core Destroys Functionality

[Altera_Forum]

Hi All, 

The Altera PCIe reference design is available at altera.com/support/refdesigns/ip/interface/ref-pciexpress-hp.html I can synthesize this design and program it on a S4GX230, without making any changes to the reference design. After programming it on the device, I can verify a link up and send/receive TLPs.    I would like to modify the PCIe IP core slightly, but before doing so, opened the "top" PCIe IP core in Megawizard and clicked "finish" without making any changes to the IP core settings. No other changes were made to the reference project files. I then resynthesized in Quartus 10.1 and programmed the device again. This time, I cannot get a link up to send/receive any TLPs.   Do you think the reference design was created with Quartus 9.x and is not possible to be regenerated in Quartus 10.1? Would there be compatible settings in Quartus 10.1's Megawizard for the PCIe IP Compiler?   Thanks.

[Altera_Forum]

There were changes to the reset logic to the PCIe core around the v10.0/1 timeframe. I just recently updated our design from 9.1 to 11.0, and it did work before the reset change, but I implemented the reset changes too after we were experiencing a link issue. The link issue turned out to be with our PCIe bridge, so I am not sure if that is your problem or not though.

[Altera_Forum]

you might take a look at the newer Qsys based PCIe designs. they are easier to follow: 

 http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs

[Altera_Forum]

try recompiling with the termination resistance on the tx pins turned off. I had issues with this before and this did the trick.

[Altera_Forum]

Thanks for the replies. It looks like there are indeed changes starting in 10.1 that affect the reset logic/ports, but even with this cleaned up, I cannot get a link up after regenerating in 10.1 

 With the latest version of Qsys, not all options in the PCIe IP core are available (max lanes, may payload, etc.).   I removed some termination settings, but still no luck.   In the end, I kept the 9.1/10.0 PCIe IP core design, and manually modified the parameters in altpcierd_example_app_chaining and top_core. They are not all explicity defined, but by going through the UG, you can figure out what the settings and parameters map to.   Hopefully in 12.0, this design will be updated AND the BFM will be included.

[Altera_Forum]

You can use the BFM from 11.0 in 11.0SP1 by overwriting one or two files. They are located in pcie_examples/common/testbench and are altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vo and possibly altpcietb_bfm_rpvar_64b_x8_gen2_pipen1b.vo for a gen2 config. We are seeing some errors reported in simulation with Txelecidle with this setup, but it appears to recover and work just fine.