Remote Update for Cyclone Reset Question and Application Image Question

[BFair2]

I have two questions:

1. The documentation states the remote update module must be reset one time I'm assuming in the factory image. In the application image i can make sure the logic doesn't activate reset. Do I need to take care in the factory image not to activate reset after the first time by reading the status bits from the remote update module?
2. It seems to me you still have to be careful not to brick the unit. In other words, if the factory image just automatically switches over to the application image on startup and the application image code has a logic error that doesn't allow you to get back to the factory image, the unit would be bricked. It seems to me that care would be needed in the factory image to have a mechanism not to load the application immediately to give you a way to reload the application image if you made a logic error. Does that make sense?

Thanks,

Brian

[ShafiqY_Intel]

Hi Brian, 1. What do you mean by “remote update module must be reset one time”? Do you mean Reconfiguration? Basically you need to have Reset State (condition: nConfig is low) after power up the device. Then, you need to have one State to toggle nConfig from ‘0’ to ‘1’and nStatus from ‘0’ to ‘1’. Once your nStatus is high, you are in Configuration-Mode. Then, you can start the status bit/read address from flash to boot up the FPGA device with Factory or Application Image. Thus, if you reconfiguration the FPGA (nconfig is toggle to ‘0’), regardless you boot up from Factory image or Application Image, you will go to Reset State again. 2. When your application image code has a logic error, the Active Serial (AS) Controller will load the same application image for 3 times before reverting back to factory image. You also have an optional feature to choose User Watchdog Timer option that can detect the functional errors in an application configuration. Kindly refer to the attachment picture for more understanding. Thanks

[ShafiqY_Intel]

😉

[BFair2]

You didn't understand either of my questions so I'll attempt to explain better.

1. In the Remote Update Intel FPGA IP UserGuide v18.0 on page 26 there is an asynchronous reset input that needs to be driven. The document states, "Asynchronous reset input to the IP core to initialize themachine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid." I can apply reset in the factory image on startup and not apply reset in the application image. My question is if due to a reconfig I leave the application image and go back to the factory image, do I have to be concerned about applying reset at startup the 2nd time in the factory image?
2. Your answer was what occurs if there is a CRC not a logic error. Assume I have application code that triggers the watchdog timer properly and loads correctly but it is either the wrong code or I accidentally messed up the logic that detects a reconfig and will never go back to the factory image. It seems like you could brick the unit. My question is to prevent that, is it important to build a mechanism into the factory image whereby it checks a flag to see if it should load the application image rather than just blindly loading it. That way even if the application image has a logic error that prevents a reconfig, you could set a flag, recycle power, and the factory image would not load the application image and could perform another update of the application image. This would prevent bricking the unit. Does that make sense?

[ShafiqY_Intel]

Hi Brian, Thanks for much clear explanation. 1. “The machine must be reset before first use, otherwise the state is not guaranteed to be valid." This statement refer to FPGA when you power up the device. When you power up your FPGA device, FPGA device did not know which state machine it at this time. Therefore, to guarantee the FPGA working according to your define State Machine, you need to toggle/press the RESET port/pin. Thus, once you toggle the RESET port/pins, FPGA will start the state machine at Reset State and work according to your define State Machine. For your case, “I can apply reset in the factory image on startup and not apply reset in the application image”, why do you apply reset in factory image? You need to understand that the RESET state is applied before configuration mode (before factory image & application image on startup). “do I have to be concerned about applying reset at startup the 2nd time in the factory image?” You only need to apply reset once after you power up the FPGA. If you do not power off the FPGA, you do not need to apply reset (FPGA already knows it current State machine, no need to reset again) 2. If you refer to the RU_RECONFIG_TRIGGER_CONDITIONS (Table 20 on page 33), you can use these condition instead of flag to prevent a reconfig. You also can use flag if you want, and it’s depend on how you design your HDL code. Thanks