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Altera_Forum
Honored Contributor I
923 Views

SD-SDI RX clock recovery

Hello, 

I am trying to implement SD-SDI core to receive SDI signals. The transmitter part works fine, however I need receiver to do the same. I have connected SDI in and out signals to create a loopback and I see that received bits are totally the same as transmitted, but has a small delay, so the data is going well. The problem is that I need to recover clear 27MHz clock for the coder chip, but the core provides only RX_CLK, which is 135MHz and rx_data_valid_out, which is data enable pin running 135MHz/5, so it doesn't work as a clock for the chip. How can I recover 50% duty cycle 27MHz clock for this purpose? 

 

Thanks.
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5 Replies
Altera_Forum
Honored Contributor I
43 Views

Solved. RX_DATA_VALID_OUT signal was sufficient to encoder chip to work as a clock. Rather workaround, than a solution.

Altera_Forum
Honored Contributor I
43 Views

in my project RX_CLK always keep "1",why?

Altera_Forum
Honored Contributor I
43 Views

How do you monitor your clock? If you are controlling it in SignalTap, using it also as the sampling clock, it will show up as a constant signal

Altera_Forum
Honored Contributor I
43 Views

Hi, Socrates 

 

I am connecting a SD-SDI receiver to a codec chip which has CCIR656 video input. 

 

There're eight pins for YCbCr input, one pin for video clock (27MHz), and one pin for data enable on the chip. 

 

Your previous reply mentioned that the "RX_DATA_VALID_OUT" should be connected to the pin of video clock. 

 

I'm wondering if I should connect the "RX_DATA_VALID_OUT" to the pin of data enable and generate a clock of 27MHz as the video clock from an external clock with a PLL in my case. 

 

From your experience, is this design correct? 

 

Thanks.
Altera_Forum
Honored Contributor I
43 Views

Basically no, it is NOT correct. That valid signal usage as clock is workaround, not a solution. The solution is to use genlock. All SDI devices must use genlock to recover the clock.

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