FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

SDI TX XCVR Failed to work

Bin_Wang
Beginner
488 Views

Hi,

  I am using the C10 GX105YF708 for SDI project.

 

For unknown reason, when I have both HDMI+SDI Tx core in the project.

The SDI tx_pll_locked and gxb_tx_ready will stay low..

HDMI TX core, IOLL_RECONFIG function will get values 0 after reconfiguration.

If I remove the HDMI core, SDI will work fine.

I am using Quartus Prime Pro 19.2.0.

SDI TX located at IO Bank 1D, Pin J28

HDMI located at IO Bank 1C, Pin AA28, AC28, AE28 and AG28

 

The reference is running as well as board booted up.

Please help me debug this weird issue.

 

Thank you!

BRs,

Bin

0 Kudos
7 Replies
CheePin_C_Intel
Employee
447 Views

Hi Bin,


As I understand it, you observe some problems with your design with the SDI TX core. Based on my understanding, there should be no dependency between HDMI and SDI cores. To further narrow down the problem, just to check with you on the following:


1. Are the CLKUSR and refclk to TX PLL to the SDI TX directly sourced from free-running oscillators on board? This is to ensure successful power up calibration.


2. From your description, seems like the tx_pll_locked stays low. We can narrow down our focus here because without the TX PLL achieving lock, the SDI TX will not work. Just to check with you which TX PLL type are you using?


3. Can you try with the latest Q21.2Pro to see if this problem persists? This is to isolate any Quartus dependent problem and any known issue which might have been fixed from Q19.2 to Q21.2 releases.


4. Is there any relation between the HDMI core and the SDI core? For example, sharing the same PLL and etc.


5. Please check through the Quartus compilation warnings to see if you can spot any anomaly ie TX PLL spacing rules violation and etc.


Please let me know if there is any concern. Thank you. 


Bin_Wang
Beginner
431 Views

Hi CheePin,

1. Are the CLKUSR and refclk to TX PLL to the SDI TX directly sourced from free-running oscillators on board? This is to ensure successful power up calibration.

  I am sure that the CLKUSR and refclk to TX PLL are free running.. 

2. From your description, seems like the tx_pll_locked stays low. We can narrow down our focus here because without the TX PLL achieving lock, the SDI TX will not work. Just to check with you which TX PLL type are you using?

Both are using fPLL, following the reference project. HDMI is using FPLL_1CB, SDI is using 1DB

3. Can you try with the latest Q21.2Pro to see if this problem persists? This is to isolate any Quartus dependent problem and any known issue which might have been fixed from Q19.2 to Q21.2 releases.

I don't have the license for new Q Pro.. 

4. Is there any relation between the HDMI core and the SDI core? For example, sharing the same PLL and etc.

No, there's no relation between HDMI and SDI..

5. Please check through the Quartus compilation warnings to see if you can spot any anomaly ie TX PLL spacing rules violation and etc.

OK, I will check.. I knew there limitation about using ATX PLL but it should work for fPLL..

 

We noticed that when the board is up, the 1st time sof downloading, SDI is not working.

But if we download the same sof again.. SDI will be back to work..

Any thought?

 

BRs,

Bin

 
Bin_Wang
Beginner
335 Views

Dear CheePin,

I have tried to compile the project in Quartus 21.2pro, but there are some error occurred. The project was set up in Quartus 19.2pro.

The error listed:

1)More than 1 positional argument specified:,0.299...

2)ERROR: An erroroccurred during automatic periphery placement...

 

I don't know whether some env need to change when using 21.2pro.

So I attached the project, could you help to give some suggestion?

Thank you.

CheePin_C_Intel
Employee
416 Views

Hi,


Thanks for your update. Regarding your latest observation on the following:


But if we download the same sof again.. SDI will be back to work.. Any thought?

[CP] Based on my experience, generally this observation happens to the system which the refclk or the CLKUSR is not available or stable during device power up. After the first power up, the XCVR is not properly calibrated and thus cannot function properly. With the second programming of the SOF, this time, the clocks are already stable, the calibration is successful and the XCVR will function properly. 


Another case of this is some of the clock oscillators are programmed by the FPGA. These clocks are only available after FPGA is in user mode.


You can try a user recalibration to the SDI TX transceiver to see if it will bring it after the first SOF downloading.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



JLee25
Novice
392 Views

Hi Chee Pin,

  I think you suggestion to do the recalibration by following the XCVR UG, right!

 

SDI did not have this interface opened by default, do you have any reference data for me?

 

Besides to download the sof twice, we also noticed if we remove the HDMI IP.

The SDI is always fine, it will start running the 1st time.

Do you think what might be wrong?

 

Thank you!

Best Regards,

Bin

CheePin_C_Intel
Employee
382 Views

Hi,


Sorry for the delay. Yes, you are right. I am referring to the XCVR user recalibration. If I understand it correctly, in C10 device, the Native PHY is a separate entity from the SDI II IP. You can perform the user recalibration through the dynamic reconfiguration AVMM interface.


As for the interference with the HDMI IP, sorry as I am not sure what might be wrong. Just wonder if you have tested using CMU PLL for the SDI and placing the SDI and HDMI in different XCVR banks just to help narrowing down the issue.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


Bin_Wang
Beginner
327 Views

Dear CheePin,

I have tried to compile the project in Quartus 21.2pro, but there are some error occurred. The project was set up in Quartus 19.2pro.

The error listed:

1)More than 1 positional argument specified:,0.299...

2)ERROR: An erroroccurred during automatic periphery placement...

 

I don't know whether some env need to change when using 21.2pro.

So I attached the project, could you help to give some suggestion?

Thank you.

 

Please refer to following link:

community.intel.com/t5/FPGA-Intellectual-Property/SDI-TX-XCVR-Failed-to-work/m-p/1320318#M24816

Reply