I use the Intel SDRAM controller described in 'ug_embedded_ip.pdf' [section 32] and found in 18.104.22.168 Open Row Management: ...
SDRAM chips are arranged as multiple banks of memory, in which each bank is capable of independent open-row address management. The SDRAM controller core takes advantage of open-row management for a single bank. Continuous reads or writes within the same row and bank operate at rates approaching one word per clock. Applications that frequently access different destination banks require extra management cycles to open and close rows.
Do this mean the controller can open only one row in one bank at a time and doesn't support interleaving read/write in two (opened) banks?
I presume you're talking about this document:
This is referencing the old SDRAM IP that only supports the old PC100 standard, not DDR. So it does not support the features you mention. If you are in fact using DDR memory, you should take a look at the modern EMIF IP which does support these features:
I want to use an old SDRAM (single data rate, no DDRx) in combination with Cyclone 10LP because of price sensitive product. But Cyclone 10 LP doesn't support DDR (unfortunately)
so I think for the combination e.g. 10CL016 + MT48LC16M16 there is no support for interleaving bank access
If you are interested to use DDR support, then I recommend you to use Cyclone 10 GX family which support DDR3 also offering a performance advantage for cost-sensitive applications. For more details, please refer to this product table: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html
If you want to use DDR3 with cheapest, the best option is using Cyclone V. In case, you want to consider using DDR2 IP, then my suggestion for you is go for Max 10 with I7 or C7 speed grade.
For more details on the device and EMIF support, you may refer to this EMIF spec : https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/exter...