Hello,I am seeting up the Altera contents for a frame grabber poject. I use a Cyclone IV GX 22 with a 4x PCIe interface. For this purpose the PCIe hard IP core is applied in the SOPC builder with a SGDMA module. The input resolution can be varied from 480p60 to 1080p60 in 28-bit TTL format. After triple buffering a logic reads it back from the RAM and pushes into the PC through the SGDMA/PCIe cores. The problem is that the SGDMA/PCIe combination is too slow. I am able to measure the ready signal of the SGDMA and found it is high for two clock cycles and low for 8. Clock frequency is 125MHz from the PCIe core. This performance is very far from our requirements. It should be at least 80% or more instead of 20%. The burst transfer is enabled and length was a varied but nothing changed. Does anybody has any experience with similar designs? I have no idea what to change. Regards, Istvan
You might want to check the latest example design.http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs You can find examples of Qsys version. Well, you can use the same idea in SOPC. Be aware, Qsys is much easier to handle those burst. You have to have same clock domain, same width, same speed in SOPC. In Qsys, Qsys fabric will take care of it.
Hi,Thanks for the advices! The root cause turned out now. The problem was that the SGDMA input was set to 32 bit while the output was 64 bit because of the input of PCI Express core. Because of this the SGDMA requested only two 32 bit words, tied them and sent to the PCIe without any burst mode. I have changed the input to 64 bit wide and it is much faster now. Unbelivable fast! I will move to Qsys to get a more stable system and better timing results. Regards, Istvan
--- Quote Start --- Hi, I have changed the input to 64 bit wide and it is much faster now. Unbelivable fast! --- Quote End --- Hello, Istvan! What OS and Driver ( custom or Altera-supplied Jungo ? ) were You using and what throughput did You achieve for Cyclone IV GX 22 with a 4x PCIe interface?