I am working with SGDMA IP (quartus 18.1) in order to transfer data from RF to SDRAM.
DMA MODE: streaming to MM.
I enabled burst transfers with maximum burst count of 32 in parameters settings of SGDMA.
Force Burst Alignment is also enable.
Maximum Transfer Length = 512KB
When I'm trying to generate write transaction from the NIOS of 500000 Bytes, the SGDMA is toggled low the output 'ready' signal towards the RF, and so I'm missing data.
The output ready signal is starting to toggled low immediately when the amount of data arrived to data_path_fifo_depth setting x2.
ex.: when my data path fifo_depth = 4096(max). I'm starting to miss data after 0x10000 bytes, even though the maximum is set to 512K.
Is there a way to solve this problem - that DMA starts toggled low and high the READY output signal exactly when it arrives to the amount of its internal FIFO data depth x2??
May I know where you got stuck ? can you give more details ? Thanks.
Below are a few points to highlight.
-for stream to memory transfer, if burst transfer is enabled, an internal write FIFO with a depth of 2x the maximum write burst size is instantiated.
Make sure that you have enough memory otherwise it may not work.
-DMA descriptors must be initialized and aligned on a 32-bit boundary.
-address should be word-aligned.
-the last descriptor in a list must have its OWNED_BY_HW but set to 0 for the SGDMA core to stop processing. Or you can generate a EOP (end of packet) in your descriptor for an unknown transfer size.
-the transfer size should be the multiple of data width for transfer without EOP.
-write burstcount signal width is between 1 to 16, so the maximum burst write size should be 32K
-Nios2 will only initiate the transfer between RF and memory by generating descriptors, and it shouldn't transfer the data.
-make sure to set the WRITE_FIXED_ADDRESS to 0 in desc_control bit map of DMA descriptor to increment the write address after each write. And set RUN to 1 in the control register bit map to start transfer.