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Altera_Forum
Honored Contributor I
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SRIO IP clock problem

SRIO IP was generated by megawizar 

tow output clocks: 

txclk and rxclk 

 

five input clocks: 

sysclk io_m_wr_clk io_m_rd_clk io_s_wr_clk io_s_rd_clk 

 

Question 1: 

I connected all of the five input clocks to the txclk, and it seems OK. 

Is it right? 

 

Question 2: 

If io_m_wr_clk, io_m_rd_clk, io_s_wr_clk and io_s_rd_clk are floating, is it OK? 

 

Question 3: 

The SRIO IP is included in a new projects. 

Should the srio.sdc file be modified for new projects 

 

thank you..
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