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SV Timing advice for QSYS PCIE_MM coreclkout

Altera_Forum
Honored Contributor I
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I wondered if anyone else has occasional timing problems with the StratixV hard IP core for PCIe Express? I'm using Gen2 4x lanes configuration and have seen this on 3 substantially different different projects. Around 5-8% of builds fail timing on the 250Mhz 'coreclkout' domain, -600ps, always between stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 and altpciexpav_stif_app:avalon_bridge|msi_addr[..] within the generated core (between hard and soft IP). The remainder are completely clean. 

 

I wondered if this is a troublesome path that others have experienced? We have very little of our own logic on the 250Mhz path, mostly stock QSYS clock crossers down to 156Mhz and our DMA core at 250. The failing builds seem to put the soft portion of the PCIe core too far into the main fabric to make the high speed paths. There's not a great deal of choice for adding pipelining the 250mhz interconnect stages in QSYS from what I can see. 

 

The output from quartus_sta looks like this: 

 

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 900mV 85C Model Setup: 'u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout' ;+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+--------------+------------+------------+; -0.596 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.838 ; 3.833 ;; -0.501 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_data ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.834 ; 3.742 ;; -0.499 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.866 ; 3.708 ;; -0.499 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.866 ; 3.708 ;; -0.496 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_data ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.841 ; 3.730 ;; -0.486 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.884 ; 3.677 ;; -0.476 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.834 ; 3.717 ;; -0.463 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG124 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.954 ; 3.584 ;; -0.463 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.837 ; 3.701 ;; -0.463 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG123 ; na385n:u0|altpcie_sv_hip_avmm_hwtcl:pcie_mm|altpciexpav_stif_app:avalon_bridge|msi_addr ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; u0|pcie_mm|altera_s5_a2p|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout ; 4.000 ; -0.837 ; 3.701 ;+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+--------------+------------+------------+  

 

Regards, 

Chris
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