Turn on suggestions

Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

Showing results for

- Intel Community
- FPGAs and Programmable Solutions
- FPGA Intellectual Property
- Sampling time and clock

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Mute
- Printer Friendly Page

Altera_Forum

Honored Contributor I

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

11-03-2010
07:12 PM

776 Views

Sampling time and clock

Hi, I want to know the relation between Sampling time (not Simulink sample time in the clock) and clock time (Real-World clock period) option. I mean real sample time of the hardware (FPGA). How can calculate the required

time per simulation timestep for the model run on FPGA. Is Real-World clock period represent the timestep of the model? In example the settings of the clock in my model are : 1. the Real-World clock period is 1nsec 2. Simulink sample time is 1. Configuration parameters settings of the model are: Start time: 1 Step time: 8000 Type: Fixed-step Solver: Discrete Fixed-step size: 1 When the model is running on FPGA I can get results (Figure) through SignalTap II Analyzer. The x-axes is starting from 1-8000. Unfortunately I don't know how can calculate the time in sec.Link Copied

3 Replies

Altera_Forum

Honored Contributor I

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

11-03-2010
08:18 PM

25 Views

Altera_Forum

Honored Contributor I

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

11-03-2010
08:20 PM

25 Views

i think you'll have some trouble trying to meet 1 ns Real World clock in an FPGA

and i like to leave Simulink time at 1, and run the simulation for "number of samples" rather than "time". you can come across rounding errors in the self-checking ModelSim simulation with odd Simulink sample times
Altera_Forum

Honored Contributor I

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

11-04-2010
07:37 AM

25 Views

For more complete information about compiler optimizations, see our Optimization Notice.