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Hi, I want to know the relation between Sampling time (not Simulink sample time in the clock) and clock time (Real-World clock period) option. I mean real sample time of the hardware (FPGA). How can calculate the required

time per simulation timestep for the model run on FPGA. Is Real-World clock period represent the timestep of the model? In example the settings of the clock in my model are : 1. the Real-World clock period is 1nsec 2. Simulink sample time is 1. Configuration parameters settings of the model are: Start time: 1 Step time: 8000 Type: Fixed-step Solver: Discrete Fixed-step size: 1 When the model is running on FPGA I can get results (Figure) through SignalTap II Analyzer. The x-axes is starting from 1-8000. Unfortunately I don't know how can calculate the time in sec.Link Copied

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i think you'll have some trouble trying to meet 1 ns Real World clock in an FPGA

and i like to leave Simulink time at 1, and run the simulation for "number of samples" rather than "time". you can come across rounding errors in the self-checking ModelSim simulation with odd Simulink sample times- Mark as New
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