Sdram high preformance MegaCore

[Altera_Forum]

Hi all, 

I am trying to create three SDRAM Mega cores controllers that will work sepratly. After creating the MegaCores I discovered that there is usage of tree pll's in my design. Could I reduce the number of pll by deriving clock's outside the MegaCore (external pll).  Thanks any way  Elad

[Altera_Forum]

The high performance cores require a PLL each. 

 Jake