Serial Lite 3 in Quartus 15?

[Altera_Forum]

Is anyone else using the Serial Lite III (SL3) IP core with Quartus 15.0? When I upgraded my QSYS project from 14.1 to 15.0 a lot of warnings appeared that I did not see in previous versions. I am suspicious that the issue being reported by these warnings is why I am unable to simulate the SL3, and why there also appear to be issues in hardware. I tried rebuilding the QSYS settings from scratch (as opposed to simply upgrading the 14.1 QSYS). I get the same problems when I do that. Here are the warning messages: 

 Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_0 cannot be automatically resolved. Valid values are: pll_freq_band0 pll_freq_band1 pll_freq_band2 pll_freq_band3 pll_freq_band4 pll_freq_band5 pll_freq_band6 pll_freq_band7 pll_freq_band8. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_1 cannot be automatically resolved. Valid values are: pll_freq_band0_1 pll_freq_band1_1 pll_freq_band2_1 pll_freq_band3_1 pll_freq_band4_1 pll_freq_band5_1 pll_freq_band6_1 pll_freq_band7_1 pll_freq_band8_1. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_fine_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {50 ps} {100 ps} {150 ps}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_ref_buf_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {1.0 ns} {2.0 ns} {3.0 ns} {4.0 ns} {5.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_0 cannot be automatically resolved. Valid values are: pll_freq_band0 pll_freq_band1 pll_freq_band2 pll_freq_band3 pll_freq_band4 pll_freq_band5 pll_freq_band6 pll_freq_band7 pll_freq_band8. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_1 cannot be automatically resolved. Valid values are: pll_freq_band0_1 pll_freq_band1_1 pll_freq_band2_1 pll_freq_band3_1 pll_freq_band4_1 pll_freq_band5_1 pll_freq_band6_1 pll_freq_band7_1 pll_freq_band8_1. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_fine_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {50 ps} {100 ps} {150 ps}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_ref_buf_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {1.0 ns} {2.0 ns} {3.0 ns} {4.0 ns} {5.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_0 cannot be automatically resolved. Valid values are: pll_freq_band0 pll_freq_band1 pll_freq_band2 pll_freq_band3 pll_freq_band4 pll_freq_band5 pll_freq_band6 pll_freq_band7 pll_freq_band8. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_1 cannot be automatically resolved. Valid values are: pll_freq_band0_1 pll_freq_band1_1 pll_freq_band2_1 pll_freq_band3_1 pll_freq_band4_1 pll_freq_band5_1 pll_freq_band6_1 pll_freq_band7_1 pll_freq_band8_1. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_fine_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {50 ps} {100 ps} {150 ps}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_ref_buf_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {1.0 ns} {2.0 ns} {3.0 ns} {4.0 ns} {5.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.native_ilk_wrapper_150_UiaZAqVKWB: When dynamic reconfiguration is enabled, users are recommended to enable multiple reconfiguration profiles for Quartus to perform robust timing closure Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_0 cannot be automatically resolved. Valid values are: pll_freq_band0 pll_freq_band1 pll_freq_band2 pll_freq_band3 pll_freq_band4 pll_freq_band5 pll_freq_band6 pll_freq_band7 pll_freq_band8. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_1 cannot be automatically resolved. Valid values are: pll_freq_band0_1 pll_freq_band1_1 pll_freq_band2_1 pll_freq_band3_1 pll_freq_band4_1 pll_freq_band5_1 pll_freq_band6_1 pll_freq_band7_1 pll_freq_band8_1. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_fine_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {50 ps} {100 ps} {150 ps}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_ref_buf_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {1.0 ns} {2.0 ns} {3.0 ns} {4.0 ns} {5.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.native_ilk_wrapper_150_UiaZAqVKWB: When dynamic reconfiguration is enabled, users are recommended to enable multiple reconfiguration profiles for Quartus to perform robust timing closure Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_0 cannot be automatically resolved. Valid values are: pll_freq_band0 pll_freq_band1 pll_freq_band2 pll_freq_band3 pll_freq_band4 pll_freq_band5 pll_freq_band6 pll_freq_band7 pll_freq_band8. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_1 cannot be automatically resolved. Valid values are: pll_freq_band0_1 pll_freq_band1_1 pll_freq_band2_1 pll_freq_band3_1 pll_freq_band4_1 pll_freq_band5_1 pll_freq_band6_1 pll_freq_band7_1 pll_freq_band8_1. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_fine_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {50 ps} {100 ps} {150 ps}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_ref_buf_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {1.0 ns} {2.0 ns} {3.0 ns} {4.0 ns} {5.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.native_ilk_wrapper_150_UiaZAqVKWB: When dynamic reconfiguration is enabled, users are recommended to enable multiple reconfiguration profiles for Quartus to perform robust timing closure Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_0 cannot be automatically resolved. Valid values are: pll_freq_band0 pll_freq_band1 pll_freq_band2 pll_freq_band3 pll_freq_band4 pll_freq_band5 pll_freq_band6 pll_freq_band7 pll_freq_band8. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_vco_freq_band_1 cannot be automatically resolved. Valid values are: pll_freq_band0_1 pll_freq_band1_1 pll_freq_band2_1 pll_freq_band3_1 pll_freq_band4_1 pll_freq_band5_1 pll_freq_band6_1 pll_freq_band7_1 pll_freq_band8_1. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_n_counter_fine_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {50 ps} {100 ps} {150 ps}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.altera_xcvr_fpll_a10_inst: The value of parameter cmu_fpll_pll_ref_buf_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {1.0 ns} {2.0 ns} {3.0 ns} {4.0 ns} {5.0 ns}. Warning: sl3_duplex_a10_9l.seriallite_iii_a10_0.native_ilk_wrapper_150_UiaZAqVKWB: When dynamic reconfiguration is enabled, users are recommended to enable multiple reconfiguration profiles for Quartus to perform robust timing closure   Is anyone else seeing this? I am really hoping that these issues get addressed, as I am having other problems using Quartus 14.1.  Thanks.