Honored Contributor II
02-25-2013 05:10 PM
Hi,I’m trying to bring-up a Transceivers link using the SerialLite II protocol between Stratix 4 (EP4SGX230KF40C2) & Arria 2 GX (EP2AGX260EF29I5) FPGAs. The FPGAs are placed on different PCBS:
- The Startix 4 is on a DE4 evaluation board.
- The boards are connected with a flat cable (on the DE4 side it is connected to the HSMB connector – J21 – on the upper third – pins 1,3 & 2,4).
- Generated the SerialLite II core and also a basic Transceivers Reconfig block, and connected them.
- I used the following configuration for the SerialLite II core:
- Data rate: 1000Mbps.
- Transfer size: 2 columns.
- Reference frequency: 100MHz.
- Bidirectional, 1 lane to each direction.
- I enabled frequency offset tolerance, though I’m not sure it is needed. I set it for 100ns.
- I didn’t change the default configuration for the Transceiver.
- Link Layer: Streaming.
- On startup, I provide the following initialization:
- The SerialLite II core’s gxb_powerdown & mreset_n are active for 4 mili-seconds.
- After 4 ms, the reset & powerdown are released, the SerialLite trains with the opposite side.
- The logic using the SerialLite core waits for a consistent “channel_up” HIGH indication (I saw that the core outputs HIGH when it is on reset, so after the reset is released the logic
- The calibration clock & reconfig clock for the transceiver are fed from a 50Mhz clock. This clock is also used to control the SerialLite II initialization discussed on 3.
- Of course – when synthesizing, I ran the TCL script for timing constraints, generated by the megawizard.