Seriallite III

[SKail]

I would like to use the IP core in my ASIC design. The IP description says it contains MAC, PCS and PMA layers. So if I buy the core, will it contain all the layers in it which I can add in to my ASIC design completely?

[Nathan_R_Intel]

Hie,

To answer your question, if you buy the IP core, it cannot be directly ported over to your ASIC design to implement MAC, PCS and PMA layers. Only the MAC and partial of the PCS are implemented in the core logic; which you can port over to ASIC. The PMA and part of the PCS is implemented using the transceivers of the FPGA which are hard circuit and not fully implemented using HDL.

Also, Seriallite III offered with the Intel FPGA was never designed with intend to be ported over to ASIC. Hence, the challenges and limitations are unknown.

Regards,

Nathan

[SKail]

Hi Nathan,

Thank you for the reply. You said a partial of PCS is implemented in the core logic. Can you specify what all blocks of PCS are included in the core?

It will help us for the design.

[Nathan_R_Intel]

My apologies for the delayed response, did not notice you have further questions. Actually, its hard to distringuish which PCS blocks are implemented partially in the core and hard PCS. Example, the block synchronizer is using the hard PCS but has some control in the core logic to ensure it meets the synchronization requirements.

You can instead look at the hard PCS instead to understand what are the blocks implemented in hard PCS. Please refer to our user guide; look for how the hard PCS blocks are used in Interlaken mode. (The PCS configuration for Serial Lite II and Interlaken are approximately similar).

SerialLite III user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_slite3_streaming.pdf

Arria 10 Phy User Guie (refer to Pg 94).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

Regards,

Nathan