Signal Tap and Quartus II FItter

[Altera_Forum]

Hi, 

 I've completed a simulation scheme and everything is working. Now I have to test it on my Altera DE2 board so i've changed my scheme with real GPIO input and a signal tap block at the end of the block diagram to check my real output. I noticed that putting only a signal tap block is not enough, because in the Signal Tap Analyzer aren't shown all the wires analyzed. The compiling till now was working.  I added a simple bus splitter with led attacched to each channel at the end of the Signal tap node...(don't ask me why , I noticed that doing so the wires appeared in the Analyzer!!). After that the complilng sequence failed, the FITTER output an error.   I guess that it was a memory problem but I wonder that it happen after adding only a bus splitter. I tried also to lower the scheme complexity but anything change.  Somebody has some practice in Signal tap?  Here I attached the new part of my scheme  http://img14.imageshack.us/img14/3153/scheme.jpg

[Altera_Forum]

Make sure that an output pin depends on the signals that are monitored by SignalTap. 

 Quartus will optimize away any logic that does not affect an output pin EVEN if you have connected it to SignalTap.  To preserve the nodes so that SignalTap can see them, use the Preserve Fan-out Free Register Node logic option.   Just something to check

[Altera_Forum]

Hi, 

I'm trying to capture a signal with the Data Conversion  HSMC Mezzanine Board connected to the Cyclone 3 FPGA dev. board.  The signal will be connected via SMA Cable to the HSMC A/D port.  I'm using the dsp builder to simulate the signal. I don't have much experience with the tool but I would like to know:  I want to use an "input block" to capture the external 14-Bit signal. I've assigned the pin of the A/D port with a Quartus II Pinout Assignment block. However: the input block still wants an input signal! What do I connect there?   I don't want to use an internal source. I will use an SMA cable from one D/A to another A/D to simulate the external signal. Can someone help me on this? I've attached the .mdl

[Altera_Forum]

Hi Beholder, 

 you should be carefull adding to much signals to the SignalTap. Depending on your clock frequency (here it is like a samplerate) the Tap could use a lot of memory bits or M9k-Blocks which normally come to an end first. After Analysis & Synthesis you can take a look in your compilation report. Here you can see how many bits go down to SignalTap, even if it is not fitted. I would slow down the frequency of your sample clock if your IOs are not so fast. When the desgin is fitted you can see how many blocks & bits are used under "RAM summary" in the compilation report.