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Hi Everyone,
Please see the 0x10 - Control register in Table 69 at this link, https://www.intel.com/content/www/us/en/programmable/documentation/lbl1415138844137.html#nik1410905615225
What is the purpose of the Descriptor_ID field? Can I put an arbitrary value in here?
Isn't the ID of the descriptor already implied by the index (or relative position) of the descriptor in the descriptor table?
When I write to RD_DMA_LAST_PTR (section 6.7.1), should I use a matching value in the Descriptor_ID field, or should I use the index of a descriptor?
Thanks,
Ari
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Hi ,
In a way your pointer is correct and the descriptor id is written by software,
should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?
>>1
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Hi ,
Can you please find the description of descriptor ID from the below document and , user have the access to write the decriptor ID from 0 to 127.
Page no: 9
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an708.pdf
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Hello RahulS_Intel,
Thanks for your reply.
I read page 9 in the doc as you instructed. Unfortunately, it didn't answer my question. My question was about the rationale of the design decision for having a Descriptor_ID field in the descriptor table. I think the field is unnecessary. This is because the offset of a descriptor from the Descriptor Base Address already gives its ID. For example, the Status portion (with "Done" bits) of the Descriptor Table does not need a Descriptor_ID field. Please see the excerpt below.
What happens if the application logic writes a "1" to the Descriptor_ID field of Descriptor 0? To start the Read DMA process for this descriptor, should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?
Thanks,
Ari
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Hi ,
In a way your pointer is correct and the descriptor id is written by software,
should the application logic writes "1" or "0" to RD_DMA_LAST_PTR ?
>>1
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Hi ,
Let me know , you need further assistance
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Hi RahulS,
I don't have any more questions, for now. Thank you very much for your help.
Ari
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Hi ,
Really glad to know .
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