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JLee25
Novice
184 Views

Simple Socket Server PCS Mode Disabled

Hi,

I am using C10 GX in custom board for TSE IP core.

My configuration is TSE + LVDS.

After download the image, the connection is not work.

From EDS, it prints out "PCS SGMII mode disabled" as attached below.Msg.pngWhere I can find information to debug this?

 

Please help!

 

Thank you!

 

BRs,

Johnson

0 Kudos
5 Replies
JLee25
Novice
59 Views

Hi,

I forgot to mentioned that I am using Quartus 19.2.0 for this build.

 

BRs,

Johnson

CheePin_C_Intel
Employee
59 Views

Hi Johnson,

 

Sorry for the delay. Thanks for your clarification. Please allow me some time to further look into it.

CheePin_C_Intel
Employee
59 Views

Hi,

 

To ensure we are on the same page, just would like to clarify if you are using HPS TSE IP or if you are using normal FPGA TSE IP? If you are using normal FPGA TSE IP, just wonder if you have had a chance to test enabling the SGMII_ENA register bit. You may refer to section 5.2.5. If_Mode Register (Word Offset 0x14) in the TSE user guide forfurther details.

 

Thank you.

JLee25
Novice
59 Views

Hi CheePin,

Thank you!

 

I will check the FPGA TSE IP core mode register as mentioned.

 

BRs,

Johnson

CheePin_C_Intel
Employee
59 Views

You are most welcome

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