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5742 Discussions

Simple VIP simulation fails

Altera_Forum
Honored Contributor I
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I have built a simple test system using SOPC and "video clocked in"->"video clocked out" blocks. I can generate the block successfully and instantiate it in a block diagram under quartus2. I can even get some results using quartus internal simulator. There is nothing else in the design expect these automatically generated bocks. 

 

But, when I simulate it under modelsim I always encounter error 

# ** Error: C:/My_Designs/uusin/alt_vip_cti_0.vhd(32): near "EOF": syntax error 

 

 

Library compilations seem to be going through without problems for all verilog files but then modelsim terminates to this EOF error.. Furthermore just by trying to compile this automatically generated file "alt_vip.." with vcom produces always the same error.  

 

This seems to be vhdl issue file even though I instructed the SOPC to use verilog..so no idea where the problems is. Anybody have any ideas? I'm using modelsim SE which supports verilog+vhdl.
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